A parallel adder which is optimal in both delay and size under left-to-right input arrival is proposed. The delay is the computation time after the arrival of the nal input bits. The proposed adder is composed of a carry select adder (CSA) and a small adder based on the on-they conversion (OTFA). Parallel computation in the CSA and the OTFA which make full use of the delay of the input arrival ...

Full Adder is one of the critical parts of logical and arithmetic units. So, presenting a low power full adder cell reduces the power consumption of the entire circuit. Also, using Nano-scale transistors, because of their unique characteristics will save energy consumption and decrease the chip area. In this paper we presented a low power full adder cell by using carbon nanotube field effect tr...

Full adders are important components in applications such as digital signal processing (DSP) architecture, and microprocessors. Over the past decade, several adiabatic logic styles have been reported. This paper deals with the design of a 1-bit full adder using adiabatic logic style (DTGAL), which are derived from static CMOS logic, without a large change. This paper also proposes a new design ...

The 1-bit full adder is a very important component in the design of application specific integrated circuits. Demands for the low power VLSI have been pushing the development of design methodologies aggressively to reduce the power consumption drastically. In most of the digital systems adder lies in the critical path that affects the overall speed of the system. So enhancing the performance of...

http: // www.ijesrt.com© International Journal of Engineering Sciences & Research Technology [200] IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY PERFORMANCE ANALYSIS OF A LOW-POWER HIGH-SPEED HYBRID 1-BIT FULL ADDER CIRCUIT AND ITS IMPLEMENTATION Swati Narang Electronics & Communication Engineering, Indira Gandhi Delhi Technical University For Women,India DOI: 10.52...

1-bit full adder circuit is a very important primitive cell in the design of Application Specific Integrated Circuits. This paper presents a novel lowpower multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charging recycling capability, this circuit has no direct connections to power supply nodes and the entire signal gates are...

Addition is a fundamental arithmetic operation which is used in different applications such as digital signal processing (DSP) and microprocessors. Single bit adder is the main component of any arithmetic circuit. This paper presents the design of new split-path Data Driven Dynamic (sp-D3L) full adder circuit. Power consumption of proposed adder varies from 0.584 nW to 2.914 nW with variation i...

This paper presents 1-bit full adder cell in emerging technologies like FinFET and CNFET that operates in the moderate inversion region for energy efficiency, robustness and higher performance. The performance of the adder is improved by the optimum selection of important process parameters like oxide and fin thickness in FinFET and number of carbon nanotubes, chirality vector and pitch in CNFE...

The terahertz optical asymmetric demultiplexer (TOAD) or semiconductor amplifier (SOA)-assisted Sagnac switches have been used to construct an all-optical 4-bit carry skip adder. This design aims satisfy the high speed and accuracy requirements of modern ultrafast digital transmission. Using a combination multiplexer full adder, we describe When compared ripple adder look-ahead may be employed ...

The most fundamental operation of any processor is the addition. For any circuit there are two important parameters that comes into count is high speed and low power consumption. Hence the speed of various modules should be maximized to dominate overall performance. Depending upon these parameters various adders can be invented like Carry Look Ahead Adder(CLA),Carry Skip Adder(CSA) and Ripple C...