Conventional scaling of gate oxide thickness, source/drain extension (SDE), junction depths, and gate lengths have enabled MOS gate dimensions to be reduced from 10μm in the 1970’s to a present day size of 0.1μm. To enable transistor scaling into the 21 century, new solutions such as high dielectric constant materials for gate insulation and shallow, ultra low resistivity junctions need to be d...

A novel uncalibrated CMOS programmable temperature switch with high temperature accuracy is presented. Its threshold temperature Tth can be programmed by adjusting the ratios of width and length of the transistors. The operating principles of the temperature switch circuit is theoretically explained. A floating gate neural MOS circuit is designed to compensate automatically the threshold temper...

We have developed a new floating-gate silicon MOS transistor for analog learning applications. The memory storage is nonvolatile; hot-electron injection and electron tunneling permit bidirectional memory updates. Because these updates depend on both the stored memory value and the transistor terminal voltages, the synapse can implement a learning function. We have derived a memory-update rule f...

We have developed a new floating-gate silicon MOS transistor for analog learning applications. The memory storage is nonvolatile; hot-electron injection and electron tunneling permit bidirectional memory updates. Because these updates depend on both the stored memory value and the transistor terminal voltages, the synapse can implement a learning function. We have derived a memory-update rule f...

A single-electron memory, in which a bit of information is stored by one electron, is demonstrated at room temperature. The memory is a floating gate metal-oxide-semiconductor transistor in silicon with a channel width ( approximately 10 nanometers) smaller than the Debye screening length of a single electron and a nanoscale polysilicon dot ( approximately 7 nanometers by 7 nanometers) as the f...

A novel linear tunable transconductor based on a combination of linearization techniques is presented. The input signal is transferred to the – conversion element by means of a high-speed feedback loop. Then, the linear – conversion is accomplished using quasi-floating-gate MOS transistors biased in the triode region. Finally, the absence of current mirrors in the signal path provides low sensi...

We have developed a complementary pair of pFET and nFET floating-gate silicon MOS transistors for analog learning applications. The memory storage is nonvolatile; hot-electron injection and electron tunneling permit bidirectional memory updates. Because these updates depend on both the stored memory value and the transistor terminal voltages, the synapses can implement a learning function. We h...

This paper describes the fabrication, and structural and electrical characterization of a new, aerosolnanocrystal floating-gate FET, aimed at non-volatile memory (NVM) applications. This aerosolnanocrystal NVM device features prograderase characteristics comparable to conventional stacked gate NVM devices, excellent endurance (>lo5 P/E cycles), and long-term non-volatility in spite of a thin bo...

A new generation method to implement CMOS floating resistors is presented. The generation method depends on the linearization of the differential current of two matched NMOS transistors in two alternative configurations. The CMOS floating resistors implemented are based on using MOS transistors operating in the saturation region with their sources connected to their substrates. New CMOS floatin...

In this article, a new structure is presented for MOS (Metal Oxide Semiconductor)-like junctionless carbon nanotube field effect transistor (MOS-like J-CNTFET), in which dual material gate with different work-functions are used. In the aforementioned structure, the size of the gates near the source and the drain are 14 and 6 nm, respectively, and the work-functions are equal and 0.5 eV less tha...