نتایج جستجو برای: floating arm

تعداد نتایج: 89632  

2017
Urs Köster Tristan Webb Xin Wang Marcel Nassar Arjun K. Bansal William Constable Oguz Elibol Stewart Hall Luke Hornof Amir Khosrowshahi Carey Kloss Ruby J. Pai Naveen Rao

Deep neural networks are commonly developed and trained in 32-bit floating point format. Significant gains in performance and energy efficiency could be realized by training and inference in numerical formats optimized for deep learning. Despite advances in limited precision inference in recent years, training of neural networks in low bit-width remains a challenging problem. Here we present th...

2012

OVERVIEW FPGAs are increasingly used as parallel processing engines for demanding digital signal processing applications. Benchmark results show that on highly parallelizable workloads, FPGAs can achieve higher performance and superior cost/performance compared to digital signal processors (DSPs) and general-purpose CPUs. However, to date, FPGAs have been used almost exclusively for fixed-point...

Journal: :CoRR 2017
Andrew Tulloch Yangqing Jia

Many applications of mobile deep learning, especially real-time computer vision workloads, are constrained by computation power. This is particularly true for workloads running on older consumer phones, where a typical device might be powered by a singleor dual-core ARMv7 CPU. We provide an open-source implementation and a comprehensive analysis of (to our knowledge) the state of the art ultra-...

Journal: :iranian journal of pharmaceutical research 0
m kouchak a badrian

a multiple-unit oral floating system was prepared using the emulsification-solvent diffusion method to prolong the gastric emptying time of theophylline. for this purpose, theophylline, ethyl cellulose and dibutyl phthalate were dissolved in an ethanol/dichloromethane mixture, added to 0.1 m hcl containing nacl (20%) or saturated theophylline and/or different concentrations of polysorbate 80 an...

2013
Murali Krishna Pavuluri Krishna Prasad

This paper presents complete processor hardware with three arithmetic units. The first arithmetic unit can perform 32-bit integer arithmetic operations. The second unit can perform arithmetic operations such as addition, subtraction, multiplication, division, and square root on 32-bit floating point numbers. The third unit can perform arithmetic operations such as addition, subtraction, multipl...

2016
Seishiro Tasaka Keisuke Matsubara Shu Nishiguchi Naoto Fukutani Yuto Tashiro Hidehiko Shirooka Yuma Nozaki Hinako Hirata Moe Yamaguchi Tomofumi Matsushita Takahiko Fukumoto Tomoki Aoyama

[Purpose] This study investigated the association between floating toe and toe grip strength. [Subjects and Methods] A total of 635 Japanese children aged 9-11 years participated in this study. Floating toe was evaluated using footprint images, while toe grip strength was measured using a toe grip dynamometer. All 1,270 feet were classified into a floating toe group and a normal toe group accor...

2005
Ronald Scrofano Ling Zhuo Viktor K. Prasanna

Due to technological advances, it has become possible to implement floating-point cores on FPGAs in an effort to provide hardware acceleration for the myriad applications that require high performance floating-point arithmetic. However, in order to achieve a high clock rate, these floating-point cores must be deeply pipelined. Due to this deep pipelining and the complexity of floating-point ari...

Journal: :physiology and pharmacology 0
fatemeh khakpay parvin rostami dept. biology, tarbiat moallem university, tehran, iran. aliasghar pilevarian

introduction: effective perception of fear signals is crucial for organism survival. when threated, the organism indicates defensive behaviors. methods: elevated plus–maze has high efficiency for measurement of fear behavior and is widly used for fear behavior determination. increase in two parameters percent of openarm entries (%oae) and percent of time spent in the open-arm (%oat) in the elev...

2007
Himanshu Thapliyal Hamid R. Arabnia Rajnish Bajpai Kamal K. Sharma

In this paper, we propose an architecture/methodology for making FPGAs suitable for integer as well as variable precision floating point multiplication. The proposed work will of great importance in applications which requires variable precision floating point multiplication such as multi-media processing applications. In the proposed architecture/methodology, we propose the replacement of exis...

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