Previous research has outlined that power dissipated during test application is substantially higher than during functional operation, which leads to loss of yield and decreases reliability. This paper shows for the first time how power is minimized in BIST RTL data paths by using power conscious test synthesis and test scheduling. According to the necessity for achieving the required test effi...

An important part of the design of complex systems is the evaluation of the large number of potential alternative designs. Due to the number and complexity of design parameters, this design space is potentially huge and very complex. Automating part of the design exploration task can be an invaluable help in finding the optimal or near optimal settings of design parameters. The choice of the mo...

This paper proposes a Design Space Exploration (DSE) framework using UML-based estimation and a multi-objective design exploration mechanism. This framework allows the designer to automatically select the most adequate modeling solution for application, architecture, and mapping, in an integrated and simultaneous way and at a very early design stage. An MDAbased transformation engine implements...

This paper describes several new algorithms for computing lower bounds on the length of the schedule and the number of functional units in high-level synthesis.

The dramatic increasing of IC technology has enabled multiple million gate FPGAs to be integrated in the same board. The performance for the large and complex custom computations can be greatly improved by implementing them in the reconfigurable hardware process elements, without enduring the huge design cost for an ASIC. However, to fully take the advantage of these hardware platforms and achi...

Hardened flip-flops and latches are designed to be resilient to soft errors, maintaining high system reliability in the presence of energetic radiation. The wealth of different hardened designs (with varying protection levels) and the probabilistic nature of reliability complicates the choice of which hardened storage element to substitute where. This paper develops an analytical model for hard...

Two-hop ad-hoc networks, in which some nodes forward traffic for multiple sources, with which they also compete for channel access suffer from large queues building up in bottleneck nodes. This problem can often be alleviated by using IEEE 802.11e to give preferential treatment to bottleneck nodes. Previous results have shown that differentiation parameters can be used to allocate capacity in a...

This paper introduces a methodology to develop energy models for the design space exploration of embedded many-core systems. The design process of such systems can benefit from sophisticated models. Software and hardware can be specifically optimized based on comprehensive knowledge about application scenario and hardware behavior. The contribution of our work is an automated framework to estim...

In the design process of computer systems or processor architectures, typically many different parameters are exposed to configure, tune, and optimize every component of a system. For evaluations and before production, it is desirable to know the best setting for all parameters. Processing speed is no longer the only objective that needs to be optimized; power consumption, area, and so on have ...

ASIPs are designed specifically for a particular application or a set of applications. Their instruction sets must be carefully tailored to provide high performance as well as to meet non-functional constraints such as silicon area and power consumption. Traditionally, evaluation of different candidate instruction sets is all carried out through simulation. However, the growing design complexit...