The aim of this work is to tackle the problem modulation wave shaping in field near communication (NFC) radio frequency identification (RFID). For purpose, a high-efficiency transmitter circuit was developed comply with strict requirements newest EMVCo and NFC Forum specifications for pulse shapes. proposed uses an outphasing modulator that based on digital-to-time converter (DTC). DTC supports...

This article proposes an interleaving switched-capacitor RF digital-to-analog converter (RFDAC) using edge combiner within the output stage to implicitly triple its effective clock carrier frequency and enable mm-wave (mmW) operation. Tripling in allows for increased energy efficiency, which is further improved by employing edge-combining-based frequency-tripling delay-locked loop (DLL) generat...

A CMOS eight-transistor (8T) memory cell is used for a complete proposed SRAM design. The proposed output buffer, eliminating the use of sense amplifier with all its synchronization schemes, exploits a cost-effective of overhead circuitry, and more important reduces the power consumption by a rate of 43% in comparing to 6T SRAM. Furthermore, the cell contributes a silicon area of 30% larger tha...

In this paper a new non-coherent architecture for GNSS tracking loops is proposed and analyzed. A non-coherent phase discriminator, able to extend the integration time beyond the bit duration is derived from the Maximum Likelihood principle and integrated into a Costas loop. The discriminator is non-coherent in the sense that the bit information is removed by using a non-linear operation. By jo...

This paper presents a variable delay line DLL circuit implemented in a 0.8 m CMOS technology. A phase detector and two charge pump circuits calibrate the delay per stage of the delay line using push-pull type clock synchronization scheme. The delay line can be programmed 6 to 18 stages. The DLL circuit is capable of reducing clock skew from 1-3ns to below 500ps for clock frequencies from 50Mhz ...

The phase-locked loop (PLL) propagation time is important unavoidable factor for high-speed coherent detection systems using broad-linewidth laser diodes. This paper report the linewidths requirements and the power penalties taking into account the loop propagation delay. The coherent optical receivers with PLL, based on Costas loop or decision driven loop (DDL) are taken into consideration. Th...

A Delay (D) flip-flop is an edge triggering device. A high speed, low power consumption, positive edge triggered conventional Delay (D) flip-flop can be designed for increasing the speed of counter in Phase locked loop, using 32nm CMOS technology. The conventional D flip-flop has higher operating frequencies but it features static power dissipation. The designed counter can be used in the divid...

This paper presents design and implementation of TDC based on time stamping using current balanced logic (CBL) buffer in 0.35 μm CMOS technology. The CBL logic buffer provides smaller delay compared to widely used current starved inverter, allowing better resolution in a given technology node. The CBL buffer based tapped delay line (TDL) provides accurate reference timing signals for time stamp...