VLSI (Very Large Scale Integration) circuits are basic components of today’s complex digital systems. In order to realize dependable digital systems, VLSI circuits should be highly reliable. VLSI testing plays an important role in satisfying this requirement. VLSI testing is to check whether faults exist in a circuit, and it consists of two main phases: test generation and test application. In ...

| This paper discusses a statistical approach to static timing analysis. Delays of gates and wires are modeled by stochastic values instead of the triple best case, typical and worst case delay. This has the advantage of avoiding the overly pessimistic (optimistic) outcome of traditional worst (best) case calculations. The paper proposes a new scheme to perform the delay calculations with stoch...

ABSTRACT The paper provides a complete analysis of the APS pixel and column circuit delay. Contrary to common belief, we show that shorter settling times can be achieved by reducing the bias current and hence reducing energy consumption. We then investigate the effect of non-idealities on the readout operation. We find that when the follower transistor channel length modulation is taken into co...

Process variations have become increasingly important as feature sizes enter the sub100nm regime and continue to shrink. Both logic and memory circuits have seen their performance impacted due to these variations. It is increasingly difficult to ensure that the circuit manufactured is in accordance with the expectation of designers through simulation. For logic circuits, general statistical sta...

We propose an exact clustering with retiming algorithm to minimize the clock period for sequential circuits. Without moving ip-ops (FF's) by retiming, conventional clustering algorithms can only handle combina-tional parts and therefore cannot achieve the best cycle time. Pan et al. 2] have proposed an optimal algorithm under the unit gate delay model. We propose a more powerful and faster algo...

This paper discusses a statistical approach to static timing analysis. Delays of gates and wires are modeled by stochastic values instead of the triple best case, typical and worst case delay. This has the advantage of avoiding the overly pessimistic (optimistic) outcome of traditional worst (best) case calculations. The paper proposes a new scheme to perform the delay calculations with stochas...

Chaotic time-delay systems are attractive candidates to generate chaotic dynamics because of their relatively simple system model. Circuit realization of the time-delay part is the main drawback of these systems. In order to overcome this drawback, a chaotic time-delay system which features a binary feedback function is presented. The use of binary feedback function results in a considerably si...

The extinction of delay fear conditioning relies on a neural circuit that has received much attention and is relatively well defined. Whether this established circuit also supports the extinction of more complex associations, however, is unclear. Trace fear conditioning is a better model of complex relational learning, yet the circuit that supports extinction of this memory has received very li...

We have implemented a four-tap adaptive lter in a continuous-time analog VLSI circuit. Since an ideal delay is impossible to implement in continuous-time hardware, we implemented the delay line as a cascade of low-pass lters (called the Gamma lter). Since many years of research in our lab has shown that the Gamma lter outperforms the delay line for a wide range of applications, the Gamma lter s...

We propose a logic synthesis system that includes power optimization after technology mapping. Our approach is unique in that our post-mapping logic transformations take into account information on circuit delay, capacitance, arrival times, glitches, etc, to provide much better accuracy than previously proposed technology-independent power optimization methods. By changing connections in a mapp...