A high accurate and low-voltage analog CMOS current divider which operates with a single power supply voltage is designed in 0.18µm CMOS standard technology. The proposed divider uses a differential amplifier and transistor in triode region in order to perform the division. The proposed divider is modeled with neural network while TLBO algorithm is used to optimize it. The proposed optimiza...

A high accurate and low-voltage analog CMOS current divider which operates with a single power supply voltage is designed in 0.18µm CMOS standard technology. The proposed divider uses a differential amplifier and transistor in triode region in order to perform the division. The proposed divider is modeled with neural network while TLBO algorithm is used to optimize it. The proposed optimiza...

an increase in energy prices will decrease the fossil fuel consumption; on the other hand, the cost-push will encourage technology improvement for firms and households. these changes will affect the emission level.this paper studies the changes of yearly pollutant emissions after an energy price reform in iran. we apply a computable general equilibrium model which consists of 7 energy goods (el...

The affordances introduced by digital technologies are reshaping consumption practices. Individuals are now engaging in networks rather than markets, and ownership-based consumption is giving way to the previously unattractive access-based, collaborative consumption. Such consumption practices produce different relationships between objects and personal identity, on which there is limited resea...

Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. We propose a novel leakage reduction technique, named “sleepy stack,” which can be applied to general logic design. Our sleepy stack approach retains exact logic state – making it...

Today, given the extensive use of convertors in industry, reducing the power consumed by these convertors is of great importance. This study presents a new method to reduce consumption power in Flash ADC in 65nm CMOS technology. The simulation results indicate a considerable decrease in power consumption, using the proposed method. The simulations used a frequency of 1 GHZ, resulting in decreas...