A design of 8 bits, 2.5V pipeline ADC is introduced in this paper. The comparator is the main improvement aiming at realizing low power dissipation. The latched comparator is adopted to achieve the specification. The design is implemented under 0.25um CMOS technology which achieves a power dissipation of 205.9mW.

As feature size and supply voltage shrink, digital calibration incorporating redundancy of flash analog-to-digital converters is becoming attractive. This new scheme allows accuracy to be achieved through the use of redundancy and reassignment, effectively decoupling analog performance from component matching. Very large comparator offsets (several LSBs) are tolerated, allowing the comparators ...

Abstrac t -Two commercial two-phase digital AC voltage sources, WW2572A from Tabor Electronics and SYS-2722 from Audio Precision, were tested for their potential use in impedance comparator bridges. The mutual relative stability of magnitudes and phase shifts of their output voltages were evaluated. Results of relative amplitude and phase shift stability measurements prove that it is possible t...

The Federal Office of Metrology and Surveying (BEV, Austria) has developed and realised a new fully automatic test System for hydrostatic weighing and determining the density of solids up to 50 kg. This volume comparator allows a full automatically determination of the volume of E1 weights and plummets in the range from 1 kg up to 50 kg through direct comparison with one single volume reference...

This paper investigates the best achievable performance by a hypothesis test satisfying a structural constraint: two functions are computed at two different terminals and the detector consists of a simple comparator checking if the functions agree. Such tests arise as part of study of fundamental limits of channel coding, and hypothesis testing with communication (rate) constraints. A simple ex...

This paper proposes an automatic, essentially domainindependent means of evaluating Spoken Language Systems (SLS) which combines software we have developed for that purpose (the "Comparator") and a set of specifications for answer expressions (the "Common Answer Specification", or CAS). The Comparator checks whether the answer provided by a SLS accords with a canonical answer, returning either ...

A binary tree based 8 bit comparator with constant delay (CD) logic is presented in this paper. The constant delay logic used in the comparator design predischarges the output to logic 0 and makes a transition to logic 1 through a critical path clocked PMOS transistor for an NMOS transistor network. This logic is twice faster than a dynamic logic gate during its D to Q operation mode for a comp...

The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution. In order to decrease circuit complexity, a comparator should maintain power, speed, resolution and offset-voltage properly. Simulations sh...

This paper describes a new online convex optimization method which incorporates a family of candidate dynamical models and establishes novel tracking regret bounds that scale with the comparator’s deviation from the best dynamical model in this family. Previous online optimization methods are designed to have a total accumulated loss comparable to that of the best comparator sequence, and exist...

A low dispersion 2-GHz comparator is an essential part of the latest automated VLSI tester by Teradyne Inc. With each new and faster CMOS logic VLSI microchips, faster and more precise comparators are needed to verify that the static discipline is being met on the many pins of the integrated circuit. As the error in the comparator is lowered, the VLSI production yield is greatly increased becau...