Memristor-based ternary content-addressable memory (TCAM) has emerged as an alternative to conventional static random-access (SRAM)-based TCAM because of its high-density integration and zero-static energy consumption. Herein, 0T2R operation on a 32 × passive memristor crossbar circuit is experimentally verified. The effective margin, which the difference between match case 1-bit mismatch case,...

Temperature has widespread and diverse effects on different subcellular components of neuronal circuits making it difficult to predict precisely the overall influence on output. Increases in temperature generally increase the output rate in either an exponential or a linear manner. Circuits with a slow output tend to respond exponentially with relatively high Q(10)s, whereas those with faster o...

In SoC design, multiple buffered clock distribution networks are typically used to drive the large clock loads of the different clock domains. Chip design involves a clock alignment step, which equalizes the delay from the clock source to each and every flop. Accurate clock alignment is important, because unwanted differences or uncertainties in clock network delays may degrade performance or c...

An area efficient technique for tuning floatinggate circuits is described. The effective threshold voltage seen from a control gate can be programmed to virtually any value. The floating-gate transistor (FGMOS) may be used to implement low-power/low-voltage digital -and/or analog circuits.

The firing rates of neurons in primate motor cortex have been related to multiple parameters of voluntary movement. This finding has been corroborated by stimulation-based studies that have mapped complex movements in rodent and primate motor cortex. However, it has been difficult to link the movement tuning of a neuron with its role within the cortical microcircuit. In sensory cortex, neuronal...

Process variations have become increasingly important as feature sizes enter the sub100nm regime and continue to shrink. Both logic and memory circuits have seen their performance impacted due to these variations. It is increasingly difficult to ensure that the circuit manufactured is in accordance with the expectation of designers through simulation. For logic circuits, general statistical sta...

We investigate two strategies for reducing the clock period of a two-phase, level-clocked circuit: clock tuning, which adjusts the waveforms that clock the circuit, and retiming, which relocates circuit latches. These methods can be used to convert a circuit with edge-triggered latches into a faster level-clocked one. We model a two-phase circuit as a graph whose vertex set V is a collection of...