Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works, must be obtained from the IEEE. Abstract Branch prediction accuracies determined using trace-driven simu...

To achieve highest performance in rapidly growing advancement in multi-core technology, there is need to minimize the large gap between faster processor speed and memory. It becomes more critical issue when branch occurs with penalty of cache miss. Many researchers proposed different branch prediction, instruction perfecting methods and algorithms but the CPU pipeline performance couldn’t be th...

Processor architectures will increasingly rely on issuing multiple instructions to make full use of available processor resources. When issuing multiple instructions on conventional processors, accurate branch prediction is critical to performance; mispredicted branches may mean that ten’s of cycles may be wasted. Architectures combining very effective branch prediction mechanisms coupled with ...

Branch Prediction is a common function in nowadays microprocessors. Branch predictor is duplicated in each core of a multi/many-core processor and makes prediction for multiple concurrent running programs respectively. To evaluate the parallel branch prediction in a multi/many-core processor, existing schemes generally use a parallel simulator running on a CPU that does not have a real massive ...

Processor architectures will increasingly rely on issuing multiple instructions to make full use of available processor resources. When issuing multiple instructions on conventional processors, accurate branch prediction is critical to performance; mispredicted branches may mean that ten’s of cycles may be wasted. Architectures combining very effective branch prediction mechanisms coupled with ...

Real-time systems require predictable processor behavior such that tight upper bounds on the worst-case execution times (WCETs) of their critical tasks can be derived. Methods for estimating these upper bounds received much attention in the last fifteen years. However, the use of high-performance processors to meet ever growing performance requirements demands the development of more and more c...

Predication of control edges has the potential advantages of improving fetch bandwidth and reducing branch mispredictions. However, heavily predicated code in out-of-order processors can lose significant performance by deferring resolution of the predicates until they are executed, whereas in nonpredicated code those control arcs would have remained as branches, and would be resolved immediatel...

The O-GEHL branch predictor has outperformed other prediction schemes using the same set of benchmarks in an international branch prediction contest, CBP-1. In this paper, we present the analysis results on each of the OGEHL branch predictor tables and also on the optimal number of predictor tables. Two methods are subsequently proposed to help increase the O-GEHL prediction accuracy. The first...

Branch target buffers (BTBs) are caches in which branch information is stored that is used for branch prediction by the fetch stage of the instruction pipeline. A typical BTB requires a few kbyte of storage which makes it rather large and, because it is accessed every cycle, rather power consuming. Partial resolution has in the past been proposed to reduce the size of a BTB. A partial resolutio...