Problem Statement: In this study, we had proposed a low power architecture for high speed multiplication. Approach: The modifications to the conventional shift and add multiplier includes introduction of modified error tolerant technique for addition and enabling of adder cell by current multiplication bit of the multiplier constant. The proposed architecture enables the removal of input multip...

In this paper, a new MBE (modified Booth encoding) recoder, and a new MBE decoder are proposed in CMOS transistor level to improve the performance of traditional multipliers. The proposed pipelined Booth multiplier can reduce the delay time of the critical path by levelizing the complex gate in the MBE decoder. As a result, MBE decoder is no more the speed bottleneck of a pipelined booth multip...

applications such as digital spectrum analyzers, digital filtering, image processing, and video transmission need to compute the Discrete Fourier Transform (DFT). A Chip architecture to compute a 64point DFT using radix-4 algorithm every 18.87 μs at 100MHz clock rate is designed. This processor incorporates static memory, controller, and combinational operating unit (COU). Input data and output...

This paper presents a bit-serial architecture for efficient addition and multiplication in binary finite fields GF( ) using a polynomial basis representation. Moreover, a low-power implementation of the arithmetic circuits and the registers is proposed. The introduced multiplier operates over a wide range of binary finite fields up to an order of . It is detailed that the bit-serial multiplier ...

We describe the design and the implementation of two three dimensional arithmetic units: a 3D adder and a 3D multiplier. Compared to their 2D counterparts, our 3D adder incurs 10.6–34.3% less delay and 11.0–46.1% less energy when the width increases from 12-bit to 72-bit; the 32×32 3D multiplier incurs 14.4% less delay and 6.8% less energy, according to the post place and route results. The pro...

Reversible logic circuits are of interests to power minimization having applications in low power CMOS design, optical information processing, DNA computing, bioinformatics, quantum computing and nanotechnology. In this paper we propose a novel 4x4 bit reversible multiplier circuit. The proposed reversible multiplier is faster and has lower hardware complexity compared to the existing counterpa...

In this paper, a high performance, high throughput and area efficient architecture of a multiplier for the Field Programmable Gate Array (FPGAs) is proposed. The most significant aspect of the proposed method is that, the developed multiplier architecture is based on vertical and crosswise structure of Ancient Indian Vedic Mathematics. As per The proposed architecture, for two 8-bit numbers; th...

This brief develops a general methodology for designing a lower-error two’s-complement fixed-width multiplier that receives two -bit numbers and produces an -bit product. By properly choosing the generalized index, we derive the better error-compensation bias to reduce the truncation error and then construct a lower error fixed-width multiplier, which is area efficient for VLSI implementation. ...

c c,-1 = f(a,,-z, ..., aora,,-1, L 2 , ..., bo, h 1 ) (4) The result is easy to show since f(u,-*, ..., a,, U,,,-,, b,n.2, ..., bo, b,,) is the first bit of l o ~ ( o ( a ) + o(p)) = logr(o(y)) = ( ~ ( c ) ) ~ , the first bit of which is cm-,. The argument is repeated for the other bits. This shows that the same f can be used to calculate each bit of the logarithmic representation of y = a + 0....