This paper presents a segment weighted random built-in self test (SWR-BIST) technique for low power testing. This technique divides the scan chain into segments of different weights. Heavily weighted segments have more biased probability than lightly weighted segments. Heavily weighted segments are placed closer to the end of scan chain than the lightly weighted segments so the scan-in transiti...

This paper describes a general technique to test external memory/caches and memory interconnects using on-chip logic. Such a test methodology is expected to significantly reduce board/system manufacturing test cost as well as to improve diagnosability of memory and memory-interconnect failures. The proposed methodology incorporates a significant amount of programmability (including programmable...

In this paper we present a new test set embedding method for test-per-clock BIST schemes. The method works efficiently with fully specified as well as partially specified test sets and requires a number of clock cycles equal to the size of the test set. The resulting test pattern generation mechanism (TPG) compares favourably in terms of area implementation and test application time to already ...

This paper presents a method for deriving a BIST specification from the initial specification of datapaths. This method minimizes BIST area overhead under test time constraint while guaranteeing a user chosen fault coverage. The designer can thus explore a wide range of solutions and keep the one that best fits with design constraints. Results show great improvements over lower level techniques.

Input vector monitoring concurrent BIST schemes are the class of online BIST techniques that overcomes the problems appearing separately in online and in offline BIST in a very effective way. This paper briefly presents an input vector monitoring concurrent BIST scheme, which monitors a set of vectors called window of vectors reaching the circuit inputs during normal operation, and the use of a...

This paper presents a new feedback shift registerbased method for embedding deterministic test patterns on-chip suitable for complementing conventional BIST techniques for infield testing. Our experimental results on 8 real designs show that the presented approach outperforms the bit-flipping approach by 24.7% on average. We also show that it is possible to exploit the uneven distribution of do...

The focus of this work is on how field programmable devices handle faults. More specifically, how physical constraints may hamper fault tolerance techniques. This paper analyzes representative work in exhaustive BIST, voting, FPTA fault tolerance, competitive runtime reconfiguration, and embryonics. Its aim is to examine how the presented techniques perform with added constraints such as space/...

A new technique for diagnosis in a scan-based BIST environment is presented. It allows non-adaptive identification of both the scan cells that capture errors (space information) as well as a subset of the failing test vectors (time information). Having both space and time information allows a faster and more precise diagnosis. Previous techniques for identifying the failing test vectors during ...

With increasing transient error rates, distinguishing intermittent and transient faults is especially challenging. In addition to particle strikes relatively high transient error rates are observed in architectures for opportunistic computing and in technologies under high variations. This paper presents a method to classify faults into permanent, intermittent and transient faults based on some...

In this paper we propose a method for evaluating test measurements for complex circuits that are difficult to simulate. The evaluation aims at estimating test metrics, such as parametric test escape and yield loss, with parts per million (ppm) accuracy. To achieve this, the method combines behavioral modeling, density estimation, and regression. The method is demonstrated for a previously propo...