This paper describes a semi-dynamic CMOS flip-flop family featuring embedded Threshold Logic functions. First, we present the concept of flip-flop featuring embedded Threshold Logic, and then we describe the circuit and its operation. Subsequently, we present the design issues and the experimental results of such Threshold Logic flip-flops, obtained in 0.25pm CMOS technology. It is shown in thi...

Flip Flops are critical timing elements in digital systems which has large impact on circuit speed and power consumption. The performance of flip flop is an important parameter to determine performance of whole synchronous circuit. In this paper, comparison of existing flip flops with different parameters is calculated. A new design a low power pulse triggered flip-flop (FF) has been proposed h...

In Integrated Circuit industry power has become a major contribution. The main attribute is the clock power in circuits of VLSI. In today’s VLSI design scenario, power utilization by clocking takes up a vital role especially in design that uses deeply scaled CMOS technology. Proficient power utilization tends to be an important constraint in modern IC design. The underneath idea of multi bit fl...

Different flip-flop designs vary in the number and complexity of logic stages they contain, and hence have different inherent parasitic delays and output drive strengths. We examine the effect of electrical load on flip-flop delay and energy consumption and show that the relative ranking of optimized flip-flop structures varies widely with both electrical effort and absolute load. We also show ...

Quantum dot cellular automata (QCA) introduces a pioneer technology in nano scale computer architectures. Employing this technology is one of the solutions to decrease the size of circuits and reducing power dissipation. In this paper, two new optimized FlipFlops with reset input are proposed in quantum dot cellular automata technology. In addition, comparison with related works is performed.Th...

Flip-flops and latches are the most important elements of a design for both a delay and energy point of view. In many electronics design low power consumption is basic need in most of the applications. The energy performance requirements enhance the most designers of next generation system towards the least possible power consumption. The power consumption is basically reduced by scaling of a p...

As the density and operating speed of CMOS VLSI chips increases, leakage power dissipation becomes more and more significant. This paper presents a leakage power behavior in Pulse triggered flip-flop. All the designs are simulated with and without the application of leakage reduction techniques and the readings are presented. By analyzing the leakage path of flip flops we propose a method to re...

Flip-Flop_1: Firstly, the old flip-flop construction that we choose to implement is the classic single edge triggered flip-flop (SETFF) which is shown in FIGURE 10.24 in the book " CMOS VLSI Design A Circuits and Systems Perspective " 4th Edition. The figure is shown below. Fig A-1 Resettable Flip-Flop The schematic that we construct is shown as follows: Fig A-2 Resettable Flip-Flop Schematic T...

Passive fiber ring resonators synchronously pumped by cw trains of ultrashort pulses are shown to exhibit polarization symmetry breaking. Application of this feature to all-optical storage is considered. The proposed storage device operates in the flip-flop mode which makes possible all-optical writing and erasing operations on individual bits. Numerical simulations suggest that a storage capac...

We describe the principle of operation of an all-optical flip-flop based on dispersive bistability in a distributed feedback semiconductor optical amplifier. Cross-phase modulation controls the photonic bandgap and Bragg resonances of the amplifier, thereby shifting the hysteresis and switching thresholds to higher or lower powers. We give the details of a simple theoretical model that is used ...