The floating-point multiplication is one of the most basic and frequent digital signal processing operations, and its accuracy and throughput greatly decide the overall accuracy and throughput of the digital signal processors. Based on vectorizing a conventional double precision multiplier, we propose a multiple precision floating-point multiplier. It supports either one double precision multip...

A bit parallel systolic multiplier in the finite field GF(2) over the polynomial basis where irreducible polynomial generate the field GF(2) is presented. The complexity of the proposed multiplier is compared in terms of area, latency and speed. The proposed multiplier has high throughput as compared with the traditional systolic multiplier. Moreover, this multiplier is highly regular, modular,...

In this paper we describe an efficient implementation of an IEEE 754 single precision floating point multiplier targeted for Xilinx Virtex-5 FPGA. VHDL is used to implement a technology-independent pipelined design. The multiplier implementation handles the overflow and underflow cases. Rounding is not implemented to give more precision when using the multiplier in a Multiply and Accumulate (MA...

Multiplier is an important key element used for arithmetic operations in digital signal processor. Power consumption in multiplier is more when compared with adders and subtractors. So reducing the power consumption of multiplier makes a digital signal processor more efficient. A Wallace tree multiplier is an efficient high speed multiplier that multiplies two integers. Here a 4*4 Wallace tree ...

In this paper we first construct the non-split extension $overline{G}= 2^{6} {^{cdot}}Sp(6,2)$ as a permutation group acting on 128 points. We then determine the conjugacy classes using the coset analysis technique, inertia factor groups and Fischer matrices, which are required for the computations of the character table of $overline{G}$ by means of Clifford-Fischer Theory. There are two inerti...

High-speed parallel multipliers are one of the keys in RISCs (Reduced Instruction Set Computers), DSPs (Digital Signal Processors), and graphics accelerators and so on. Array multiplier, Booth Multiplier and Wallace Tree multipliers are some of the standard approaches used in implementation of binary multiplier which are suitable for VLSI implementation. A simple digital multiplier (henceforth ...

Motivated by recent analytical and numerical work on two-and three-dimensional convection with imposed spatial periodicity, we analyse three examples of bifurcations from a continuous group orbit of spatio-temporally symmetric periodic solutions of partial differential equations. Our approach is based on centre manifold reduction for maps, and is in the spirit of earlier work by Iooss (1986) on...

This paper presents low power 8x8 bit multipliers which are implemented with Tanner Tool v13.0 at 500MHz frequency with 65nm technology which is having a supply voltage 1.0v. There are different CMOS multiplier circuits are analyzed names as Braun multiplier, Wallace tree multiplier, Row bypass Braun multiplier, Column bypass Braun multiplier, Row and Column bypass Braun multiplier and these mu...

The purpose of this note is to describe how central multiplier theorems for compact Lie groups can be reduced to corresponding results on a maximal torus. We shall show that every multiplier theorem for multiple Fourier series gives rise to a corresponding theorem for such groups and, also, for expansions in terms of special functions. We use the notation and terminology of N. J. Weiss [4]. Let...

The Wallace Multiplier is mainly used in the Arithmetic & Logic Unit (ALU) to perform the scientific computation in processors, controller etc... The existing multiplication technique like booth multiplier, array multiplier etc requires more time in multiplications. Hence Wallace Multiplier has been designed by using the parallel process to reduce the delay. The regular Wallace Multiplier requi...