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تعداد نتایج: 35601 فیلتر نتایج به سال:
D. C. Nunes, R. J. Phillips, G. Picardi, J. J. Plaut, A. Safaeinili, R. Seu, and A. Egan. Lunar and Planetary Institute, Houston, TX 77058 ([email protected]), Department of Earth and Planetary Sciences and McDonnell Center for the Space Sciences, Washington University, Saint Louis, MO 63130, Infocom Department, “La Sapienza” University of Rome, 00184 Rome, Italy, Jet Propulsion Laboratory, Pa...
With the development of satellite communications, on-board processing (OBP) obtains more and more attentions due to the increased efficiency and performance. However, the large amounts of digital circuits in the OBP transponders are sensitive to the high-energy particles in space radiation environments, which may cause various kinds of single event effect. Among these effects, single event upse...
Immune interactions in the heart were studied using a murine model of myosin-induced autoimmune myocarditis. A T cell hybridoma specific for mouse cardiac myosin was generated from A/J mice and used to demonstrate that endogenous myosin/I-Ak complexes are constitutively expressed on antigen-presenting cells in the heart. This T cell hybridoma, Seu.5, was used as a functional probe to identify a...
This paper presents the development of a set of tools and the associated methodology for performing pulsed laser fault injection experiments in SRAM-based FPGAs. The new platform allows reliable evaluation of the impact of SEU and MBU in the configuration memory.
We measured neutron-induced SEUs (Single Event Upsets) and MCUs (Multiple Cell Upsets) on FFs in a 65 nm bulk CMOS process. Measurement results show that maximum MCU / SEU ratio is 30.6% and is exponentially decreased by the distance between latches on FFs.
Single event upsets (SEU) produced by heavy ions in SOI CMOS SRAM cells were simulated using a mixed-mode approach, that is, two-dimensional semiconductor device simulation by TCAD tool coupled with circuit SPICE simulator. The effects of parasitic BJT and particle strike position on the SOI CMOS SRAM cells upset for transistor length scaling from 0.25 um to 65nm are presented.
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