TEST PATTERN GENERATION USING LFSR WITH RESEEDING SCHEME FOR BIST DESIGNS Leeba Varghese, Suranya G Electronics and Communication Department/ MG University MG University/ Ilahia College of Engineering and Technology Ilahia College of Engineering and Technology Mulavoor P.O, Muvattupuzha Pin: 686673 Kerala India ____________________________________________________________________________________...

Error correction is one of the important technique for detecting and correcting errors in communication channels, memories etc., Errors are associated with all types of memories. But the NAND FLASH memories are competing in the market due to its low power, high density, cost effectiveness and design scalability. As far as the memory is concerned the testing should not consume more time. So, som...

Modular reduction is the basic building block of many publickey cryptosystems. BCH codes require repeated polynomial reductions modulo the same constant polynomial. This is conceptually very similar to the implementation of public-key cryptography where repeated modular reduction in Zn or Zp are required for some fixed n or p. It is hence natural to try and transfer the modular reduction expert...

A Linear Feedback Shift Register, or LFSR, can implement an event counter by shifting whenever an event occurs. A single two-input exclusive-OR gate is often the only additional hardware necessary to allow a shift register to generate, by successive shifts, all of its possible nonzero values. The counting application requires that the number of shifts be recoverable from the LFSR contents so th...

‧Protecting elliptic curve cryptography against memory disclosure attacks ‧A guess-then-algebraic attack on LFSR-based stream ciphers with nonlinear filter ‧ How to compare selections of points of interest for side-channel distinguishers in practice

We present simple and efficient hash functions applicable to secure authentication of information. The constructions are mainly intended for message authentication in systems implementing stream cipher encryption and are suitable for other applications as well. The proposed hash functions are implemented through linear feedback shift registers and therefore attractive for hardware applications....

This paper presents a new approach for on-chip test pattern generation. The set of test patterns generated by a pseudo-random pattern generator (e.g., an LFSR) is transformed into a new set of patterns that provides the desired fault coverage. The transformation is performed by a small amount of mapping logic that decodes sets of patterns that don’t detect any new faults and maps them into patt...

We have considered implementation of parallel test pattern generator based on a linear feedback shift register (LFSR) with multiple outputs used as a building block in built-in-self-test (BIST) design within SoC. The proposed design can drive several circuits under test (CUT) simultaneously. The mathematical procedure for concurrent pseudo random number (PRN) generation is described. We have im...

CMOS stands for Complementary Metal Oxide Semiconductor. It is basically a class of integrated circuits, and is used in a range of applications with digital logic circuits, such as microprocessors, microcontrollers, static RAM, etc. It is also used in applications with analogue circuits, such as in data converters, image sensors, etc. There are quite a few advantages that the CMOS technology ha...