The paper describes the Low power 32-bit encrypted MIPS processor based on AES algorithm and MIPS pipeline architecture. The pipeline stages of MIPS processor are arranged in such a way that pipeline can be clocked at high frequency and clock gating technique is used for reducing power consumption. Encryption blocks of Advanced Encryption Standard (AES) cryptosystem and dependency among pipelin...

Pipeline is a standard way of decomposing an operation into concurrently operating stages to increase throughout at a moderate increase in area. Pipeline can be implemented both synchronously and asynchronously. In a synchronous pipeline the global clock regulates the communication of data between stages. In asynchronous pipeline the communication of data between stages is regulated by local co...

The pipeline route selection process focuses on achieving the optimal location for a pipeline. Even though this is the desired process outcome, in reality it is counter to data and information collection efforts that are concentrated on identifying and inventorying locations for pipeline avoidance. Changing and aligning the routing mindset from output (pipeline route) to input (discipline infor...

Pipeline parallelism organizes a parallel program as a linear sequence of stages. Each stage processes elements of a data stream, passing each processed data element to the next stage, and then taking on a new element before the subsequent stages have necessarily completed their processing. Pipeline parallelism is used especially in streaming applications that perform video, audio, and digital ...

This paper presents a clocking pipeline technique referred to as a single-pulse pipeline (PP-Pipeline) and applies it to the problem of mapping pipelined circuits to a Field Programmable Gate Array (FPGA). A PP-pipeline replicates the operation of asynchronous micropipelined control mechanisms using synchronous-orientated logic resources commonly found in FPGA devices. Consequently, circuits wi...

In this paper, an asynchronous pipeline instruction simulator, ARAS is presented. With this sim-ulator, one can design selected instruction pipelines and check their performance. Performance measurements of the pipeline connguration are obtained by simulating the execution of benchmark programs on the machine architectures developed. Depending on the simulation results obtained by using ARAS, t...

This project presents a high-throughput and ultralowpower asynchronous domino logic pipeline design method, targeting to latch-free and extremely fine-grain or gate-level design. The data paths are composed of a mixture of dual-rail and single-rail domino gates. Dual-rail domino gates are limited to construct a stable critical data path. Based on this critical data path, the handshake circuits ...