In digital VLSI system the clock distribution network and flip flops are most power consuming components. The reduction of power consumption by clock distribution networks & flip flop makes the total VLSI system as low power VLSI system. In the earlier VLSI system design, different power consumption methods are followed to design the various flip-flops .The SABFF(sense amplifier based flip flop...

قدرت تفکیک دستگاه طیف‌نگار جرمی به صورت مستقیم شدت یون خروجی و انرژی آن بستگی دارد. مقدار تولید شده جریان باریکه الکترونی وابسته است. از جمله وظایف مدار کنترل چشمه برخورد تنظیم برای رسیدن بهینه می‌باشد. در ساخت پارامترهایی نظیر تثبیت آن، دقیق پتانسل الکتریکی لنز الکترودهای یونی بسیار حایز اهمیت این مقاله با قابلیت انتشار الکترون، پتانسیل نقاط طراحی ساخته شد. کنترلر بر روی طیف نگار 44Varian MAT ...

Our daily lives heavily depends on the social information infrastructure, which includes a huge numbers of VLSI chips. Various system failures are caused by physical faults in the circuits, human errors in design/fabrication/operation and malicious attacks. In this paper, the causes and countermeasures of failures of VLSI are summarized. The discussion leads a new direction of researches of des...

It is well-known that all Boolean functions of n variables can be computed by a logic circuit with o(2n/n) gates (Lupanov's theorem) and that there exist Boolean functions of n variables which require logic circuits of this size (Shannon's theorem). We present corresponding results for Boolean functions computed by VLSI circuits, using Thompson's model of a VLSI chip. We prove that all Boolean ...

In the 80s of last century, integrated injection logic (I2L) was widely used as an elementbase. Somewhat later, in development I2L, injection-field (IPL) appeared for constructionof VLSI. Both element bases are close degree integration on a chip. An increase inthe into VLSI can be achieved using self-displacement regions, which theintroduction impurities different types is carried out single bo...

A systolic serial multiplier for unsigned numbers is presented which operates without zero words inserted between successive data words, outputs the full product and has only one clock cycle latency. The multiplier is based on a modified serial/parallel scheme with two adjacent multiplier cells. Systolic concept is a well-known means of intensive computational task through replication of func...

A systolic serial multiplier for unsigned numbers is presented which operates without zero words inserted between successive data words, outputs the full product and has only one clock cycle latency. &#10The multiplier is based on a modified serial/parallel scheme with two adjacent multiplier cells. Systolic concept is a well-known means of intensive computational task through replication of fu...

A new very large scale integration (VLSI) algorithm for a 2N-length discrete Hartley transform (DHT) that can be efficiently implemented on a highly modular and parallel VLSI architecture having a regular structure is presented. The DHT algorithm can be efficiently split on several parallel parts that can be executed concurrently. Moreover, the proposed algorithm is well suited for the subexpre...