Hardware Description Languages (HDL) like VHDL are widely used to design and simulate with programmable logic devices. Simulation of very large scale integrated digital systems (VLSI) is of great importance as it assures system correctness and maximizes system performance ([4], [5], [9]). The utilization of parallel simulation introduces the problem of how to partition the logic gates and syste...

This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Altera Quartus II software is used for simulation and optimization of the synthesizable VHDL code. The set o...

In hardware design of today, there is a growing usage of hardware design languages to speed up the time-to-market. As the design complexity grows, so does the simulation time. To solve this problem, several research groups have suggested the use of parallel computers to speed up simulation. This report surveys some of the issues involved when designing a parallel simulator for one of the more p...

VHDL is the one of the most important and widely used hardware description languages at this time. The increase in size and complexity of VHDL models necessitates the use of parallel and distributed algorithms to obtain acceptable simulation performance. We have investigated the use of optimistic distributed algorithms with VHDL simulation. Using an optimistic algorithm with VHDL introduces som...

In a top-down, language-based design methodology, requirements can be specified in an executable format, reducing the ambiguity typically encountered with written requirements, and serving as the starting point for the evolution of more detailed requirements and design specifications. As part of the Rapid Prototyping of Application Specific Signal Processors (RASSP) program, a VHDL executable r...

We present a mathematical de nition of a hardware description language that admits a semantics-preserving translation to a subset of VHDL. The language is based on the VHDL model of event-driven simulation and includes behavioral and structural circuit descriptions, the basic VHDL propagation delay mechanisms, and both zero and nonzero delays. It has been formally encoded in the computational l...

This paper describes the initial development of a translator from VHDL-AMS code into HSPICE, as a contribution to the group of CAD-EDA tools in the field of analog design. Analog synthesis tools are not as developed as digital ones but the arise of VHDLAMS, a superset of VHDL, can help to their development. In this work, we present some features of a translator capable to synthesise analog circ...

To perform cosimulation, an interface design of VHDL simulation is needed. This interface is responsible for communicating packets between any VHDL simulator and the cosimulation backplane, PeaCE, which is a Ptolemy extension as codesign environment. The interface also manages the simulation for correct timed cosimulation. By the automatic interface generation mechanism, the interface is genera...

This paper gives operational semantics for a subset of VHDL in terms of abstract machines. Restrictions to the VHDL source code are the niteness of data types, and the absence of quantitative timing infor-mations. The abstract machine of a design unit is built by composition of the abstract machines for its embedded processes and blocks. The kernel process in our model is distributed among the ...

We present an application tool dedicated to superconducting circuits design. Based on the use of VHDL-AMS language on System Vision software, we developed an innovating approach with top-down methodology to specify the RSFQ circuits. We take the example of a sigma-delta bandpass ADC and show the different processes used to design it. The demonstration shows the complete system in mixed signal l...