نتایج جستجو برای: حافظه dram
تعداد نتایج: 6485 فیلتر نتایج به سال:
This paper describes a performance examination of the DDR2 DRAM architecture and the proposed cache-enhanced variants. These preliminary studies are based upon ongoing collaboration between the authors and the Joint Electronic Device Engineering Council (JEDEC) Low Latency DRAM Working Group, a working group within the JEDEC 42.3 Future DRAM Task Group. This Task Group is responsible for develo...
-Ihis paper presents a testable design of dynamic randomaccess memory (DRAM) architecture which allows one to access multiple cells in a word l i e simultaneously. The technique utilizes the two-dimensional (2D) organization of the DRAM and the resulting speedup of the conventional algorithms is considerable. This paper specifically investigates the failure mechanisms in the three-dimensional (...
Resistance switching random access memory (RRAM) has drawn considerable attention for the application in nonvolatile memory element in semiconductor memory devices. A ZnO thin film now assumed to be useful for dynamic random access memory (DRAM) cell. In this paper we provide a framework to its use as a switching ON or OFF in DRAM cell. In this type of memory cell the ZnO thin film has a lot of...
Routers are the prevalent type of network nodes in today’s Internet. A router processes incoming packets and forwards them towards their destination. Core routers, i. e., routers that operate in the core of the Internet, contain up to hundreds and more ports to be able to interconnect many network segments. Temporary unbalanced traffic between the ports of a router can lead to overload situatio...
2D numerical simulations are used to demonstrate the Z-FET as a competitive embedded capacitor-less DRAM cell for low-power applications. Experimental results in 28 nm FD-SOI technology are used to validate the simulations prior to downscaling tests. Default scaling, without any structure optimization, and enhanced scaling scenarios are considered before comparing the bit cell area consumption ...
DRAM row buffer conflicts can increase the memory access latency significantly for single-threaded applications. In a chip multiprocessor system, multiple applications competing for DRAM will suffer additional row buffer conflicts due to interthread interference. This paper presents a new hardware and software cooperative DRAM bank partitioning method that combines page coloring and XOR cache m...
The trade-off in designing merged DRAM logic (MDL) is explored for video signal processing. Computing requirements and memory bandwidths are quantitatively analyzed in the programmable MDL architecture. The number of processing elements (NPE) and the number of bus width (NBW) are obtained as a function of macro block rate, clock frequency, data rate, and number of clock/memory access cycles. Op...
This paper presents an irredundant encoding technique to minimize the switching activity on a multiplexed Dynamic RAM (DRAM) address bus. The DRAM switching activity can be classified either as external (between two consecutive addresses) or internal (between the row and column addresses of the same address). For external switching activity in a sequential access pattern, we present a power-opt...
To limit the exponential complexity required to analyze the dynamic faulty behavior of DRAMs, algorithms have been published to approximate the faulty behavior of DRAM cell defects. These algorithms, however, have limited practical application since they are based on generic memory operations (writes and reads) rather than the DRAM specific operations (activation, precharge, etc.). This paper e...
We present the design of a high performance on-chip pipelined asynchronous DRAM suitable for use in a microprocessor cache. Although traditional DRAM structures suffer from long access latency and even longer cycle times, our design achieves a simulated core sub-nanosecond latency and a respectable cycle time of 4.8ns in a standard 0.25um logic process. We also show how the cycle time penalty c...
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