This paper presents a wide range of algorithms and architectures for computing the 1-D and 2-D Discrete Wavelet Transform (DWT), and the 1-D and 2-D Continuous Wavelet Transform (CWT). The algorithms and architectures presented here are independent of the size and nature of the wavelet function. New on-line algorithms are proposed for the DWT and the CWT which require signiicantly small storage...

[Article] Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding VLSI co-processors for real-time high-quality H.264/AVC video coding. Porto, the institutional repository of the Politecnico di Torino, is provided by the University Library and the IT-Services. The aim is to enable open access to all the world. Please share with us how this access benefit...

The most powerful channel coding schemes, namely those based on turbo codes and low-density parity-check (LDPC) Gallager codes, have in common the principle of iterative decoding. However, the relative coding structures and decoding algorithms are substantially different. This paper presents a 2048-bit, rate-1/2 soft decision decoder for a new class of codes known as Turbo Gallager Codes. These...

In this paper highly concurrent pipelined computing structures based on a constrained digital contour smoothing are described. The smoothing minimizes the undersampling, digitizing and quantizing error and so it is able to improve the stability of invariants calculation. The word-level and bit-level systolic arrays for completely pipelined calculation of the constrained least-squares digital co...

Conventional full-custom reconfigurable logic device design and implementation are time consuming processes. In this research, we propose a design framework in order to improve FPGA IP core design efficiency by link academic FPGA design flow and commercial VLSI CADs based on the synthesizable method. A novel FPGA routing tool is developed in this framework, namely the EasyRouter. By using simpl...

We present a class of analog cellular automata for parallel analog random vector generation, including theory on the randomness properties, scalable parallel very large scale integration (VLSI) architectures, and experimental results from an analog VLSI prototype with 64 channels. Linear congruential coupling between cells produces parallel channels of uniformly distributed random analog values...

High performance architectures for the data intensive and latency restrained applications can be achieved by maximizing both parallelism and pipelining. In this paper, the CORDIC based hardware primitives of 3-D rotation with high throughput 3-D vector interpolation are presented. The proposed architecture for 3-D vector interpolator, which is based on the redundant CORDIC arithmetic, has been ...

This paper summarizes two graduate-level class projects in EE201A/EE298 (VLSI Architectures and Design Methods) at the University of California, Los Angeles (UCLA). The purpose of the class is to explore the impact of system-level optimization for various target platforms using EDA.

Some techniques for low power operation in VLSI using the lowest possible supply voltage coupled with an architectural optimization have shown that we can save power even i f we increase silicon area [7]. In this paper we present a strategy to reduce power consumption in FPGAs based on pipeline architectures working with a low supply voltage.

A stabilized parallel algorithm for direct-form recursive filters is obtained using a new method of derivation in the Z domain. The algorithm is regular and modular, so very efficient VLSI architectures can be constructed to implement it. The degree of parallelism in these implementations can be chosen freely, and is not restricted to be a power of two.