Capacitive pick-ups for closed-orbit measurements are presently under development for an Ultra-low energy Storage Ring (USR) at the future Facility for Low-energy Antiproton and Ion Research (FLAIR). Low-intensity, low-energy antiprotons impose challenging demands on the sensitivity of the monitoring system. The nondestructive beam position monitors (BPMs) should be able to measure about 10 par...

Abstract: In this paper we present a novel static differential ultra low-voltage (ULV) CMOS logic style. Simulated data for the logic style is presented and compared to related ULV logic styles and complementary CMOS gates. The proposed logic style is aimed for high speed serial adders in ultra low-voltage applications. In terms of energy delay product (EDP) the logic style offers a significant...

As technology advances to giga-scale integration level, global interconnect resource becomes increasingly valuable in a VLSI chip. This is due to the exponential growth of the total number of interconnects/wires as the feature size of MOS transistors decreases in scaled deep submicron CMOS technologies. Interconnect length, however, has not scaled down with feature size and remains long relativ...

The application of ultra-wideband (UWB) technology to low-cost short-range communications presents unique challenges to the communications engineer. The impact of the US FCC’s regulations and the characteristics of the low-power UWB propagation channels are explored, and their effects on UWB hardware design are illustrated. This tutorial introduction includes references to more detailed explora...

As technology advances to giga-scale integration level, global interconnect resource becomes increasingly valuable in a VLSI chip. This is due to the exponential growth of the total number of interconnects/wires as the feature size of MOS transistors decreases in scaled deep submicron CMOS technologies. Interconnect length, however, has not scaled down with feature size and remains long relativ...