A robust physical design of 3D-IC requires investigation on through-silicon-via (TSV). The large temperature and stress gradients can severely affect TSV delay with large variation. The traditional physical model treats TSV as resistor with linear electrical-thermal dependence, which ignores the fundamental device physics. In this paper, a physics-based electrical-thermal-mechanical delay model...

AIM To evaluate the effectiveness and safety of high-speed (5,000 cuts per minute) 23 G transconjunctival sutureless vitrectomy (TSV) in severe diabetic fibrovascular proliferation (DFVP). PATIENTS AND METHODS In this retrospective consecutive case series, patients who underwent 23 G TSV for severe DFVP between October 2011 and March 2014 at our institution were evaluated. 23 G TSV was perfor...

The use of the 2-(4-methylphenylsulfonyl)ethenyl (tosvinyl, Tsv) group for the protection of the NH group of a series of imides, azinones (including AZT), inosines, and cyclic sulfonamides has been examined. The Tsv-protected derivatives are obtained in excellent yields by conjugate addition to tosylacetylene (ethynyl p-tolyl sulfone). The stereochemistry of the double bond can be controlled at...

BACKGROUND Three human polyomaviruses have been classified as probable (Merkel cell polyomavirus) or possible (BK and JC polyomaviruses) carcinogens, but few epidemiologic studies have examined associations between this growing class of viruses and risk of non-Hodgkin lymphoma (NHL). METHODS Associations between polyomavirus antibodies and NHL incidence were examined using data from the Ameri...

The main methodologies and recent patents on test wrapper design have been reviewed in this paper. The design of three-dimension test wrapper for IP module in System on Chip is a NP Hard problem. As the test time of an IP module is determined by the longest wrapper scan chain and each TSV has area costs and is a potential source of defects, it is necessary to shorten the longest wrapper chain a...

Through silicon via (TSV) offers a promising solution for the vertical connection of chip I/O, which enables smaller and thinner package sizes cost-effective products by using wafer-level packaging instead chip-level process. However, TSV leakage has become critical concern in BEOL In this paper, Cu-fulfilled via-middle with 100 µm depth embedded 0.18 CMOS process sensor application is presente...

In this paper, a thermal-stress coupling optimization strategy for coaxial through silicon via (TSV) is developed based on the finite element method (FEM), artificial neural network (ANN) model and particle swarm (PSO) algorithm. order to analyze effect of design parameters distribution TSV, FEM simulations TSV are conducted by COMSOL Multiphysics. The structure symmetric. mapping relationships...

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

sunflower, (helianthus annuus) is considered as an important oilseed crop grown in many countries including iran. in recent years, tobacco streak virus (tsv) has been found in sunflower fields in iran. tsv is a type member of ilarviruses, and infects a wide range of crops as well as weeds. in this survey and during 2008, two isolates of sunflower and one isolate of faba bean collected from, ira...

In this work, the effect of copper through-silicon via (TSV) interconnect diameter on stress buildup in Cu TSVs was experimentally determined using a synchrotron-based X-ray microdiffraction technique. A single chip with different Cu TSV diameters (3, 5, and 8 lm), all having the same depth and processing conditions was studied. Prior to the measurements, the chip was annealed at 420 C (30 min)...