Based on the understanding of flicker noise generation in “silicon metal-oxide semiconductor field-effect transistors” (MOSFETs), a novel method for improving the phase noise performance of a CMOS LC oscillator is presented. Zhou et al. and Hoogee have suggested that the 1 noise can be reduced through a switched gate, and the flicker noise generated is inversely proportional to the gate switchi...

Pass-Transistor Mapper (PTM), a logic synthesis tool speci cally designed for passtransistor based logic library that has only three basic cells, is reported. It exploits the close relationship between BDD representation of logic and the structure of pass-transistor logic cells to ensure e cient technology mapping. BDD variable order optimization is achieved through a genetic algorithm with dyn...

CMOS integrated circuit analysis and design is a fast paced field which deals with many advanced technologies and a difficult skill for many students in a comprehensive first course in Microelectronics. New methods and techniques to help novices learn are needed. In this paper the transistor role concept is used and common individual CMOS transistor roles are identified. Typical circuit and blo...

This paper experimentally investigates the effectiveness of regularly-placed bit-slice layout and transistor-level optimization to datapath circuit performance. We focus on cell-base design flows with transistorlevel circuit optimization. We examine the effectiveness through design experiments of 32-bit carry select adder and 16-bit tree-style multiplier in a 0.35μm technology. From the experim...

The fabrication and measurements of solution-processed vertically stacked complementary organic field-effect transistors (FETs) with a high static noise margin (SNM) are reported. In the device structure, a bottom-gate p-type organic FET (PFET) is vertically integrated on a top-gate n-type organic FET (NFET) with the gate shared in-between. A new strategy has been proposed to maximize the SNM b...

The layout s y n t h e s i s for pass transistor c e l l s (PTCs) i s different from that for CMOS c e l l s because o f the various s i z e s o f transistors used in a PTC and the imbalance i n the number o f pMOS and nMOS transis tors . This makes i t d i f f icult t o app ly c o m m o n l y used l inear transistor placement t o PTC layout . Moreover, the mixed placement with CMOS cel ls rest...

1. Introduction The global need for high performance and low power computing continues to be a major driver of the semiconductor industry. In the high performance computing segment, complex projects (such as medical imaging, genomics research and weather prediction) need significant performance increases to fulfill growing expectations. The core computing segment requires performance increases ...

High speed and low power consumption are vital in ICs for high-speed optical communications systems. Some of the competing IC elements in this field include: Si-BJT (Silicon Bipolar Transistor), Si-CMOS (Silicon Field Effect Transistor), SiGe-BJT (Silicon Germanium Bipolar Transistor), GaAs-HBT (Gallium Arsenide Heterobipolar Transistor), GaAs-FET (Gallium Arsenide Field Effect Transistor), and...

is desirable ‘in many k.J high-frequency and switching applications of transistors. A single transient response measurement can, in principle, yield frequency response information over a range of frequencies of width determined by the short-time resolution of the transient response measurement and the duration of the measurement. Further, measurement of the response to a unit step or unit impul...

In order to reduce on state resistance of LDMOS transistor, it is necessary to use RESURF structure. However, conventional isolated RESURF structures cannot be used in a multi power BCD process because of the breakdown voltage dependence on epi thickness. Accordingly, we had to use non RESURF LDMOS transistor that has higher on state resistance than RESURF LDMOS transistor in a multi power BCD ...