In this paper we outline a procedure to determine appropriate partitioning of programmable logic and interconnect area to minimize overall device area across a broad range of benchmark circuits. To validate our design approach, FPGA layout tools which target devices with less that 100% logic capacity have been developed to augment existing approaches that target fully-utilized devices. These to...

There is currently great interest in using fixed arrays of FPGAs for logic emulators, custom computing devices, and software accelerators. An important part of designing such a system is determining the proper routing topology to use to interconnect the FPGAs. This topology can have a great effect on the area and delay of the resulting system. Tree, Bipartite Graph, and Mesh interconnection sch...

This paper presents the design and implementation of a programmable Finite Impulse Response (FIR) Filter using ALTERA Field Programmable Gate Array (FPGA) device. The filter performance is first tested using Filter Design and Analysis (FDA) tool from Mathworks to verify magnitude response and obtain coefficient tables. The test operation includes LPF and BPF filter types with coefficient length...

This paper focuses on the design of a low power and high performance FPGA based Digital Space Vector Pulse Width Modulation (DSVPWM) controller for three phase voltage source inverter. A new method is proposed to realize easy, accurate and high performance DSVPWM technique based on FPGA with low resource consumption and reduced execution time than conventional methods. Equations of SVPWM are re...

<span>This paper presents the FPGA-based implementation of compact montgomery modular multiplier (MMM). MMM serves as a building block commonly required in security protocols relying on public key encryption. The proposed design is intended for hardware applications lightweight cryptographic modules that utilized system chip (SoC) and internet things (IoT) devices. modification structure ...

In this paper, we present a configurable FPGA-based hardware architecture for adaptive processing of noisy signals for target detection based on Constant False Alarm Rate (CFAR) algorithms. The architecture has been designed to deal with parallel processing and to be configured for three versions of CFAR algorithms, the Cell-Average, the Max and the Min CFAR. The proposed pipelined architecture...

In this paper, a central pattern generator (CPG) model based on asynchronous coupling of cellular automaton (CA) phase oscillators for hexapod robot is presented. The presented CPG composed the CA whose discrete state transitions are triggered by multiple clocks. Then, evaluation functions to quantify synchronization states target gait patterns in introduced. Analyzing synchronizations using fu...

The design space of FPGA-based processor systems is huge, because many parameters can be modified at designand runtime to achieve an efficient system solution in terms of performance, power and energy consumption. Such parameters are, for example, the number of processors and their configurations, the clock frequencies at design time, the use of dynamic frequency scaling at runtime, the applica...

The concept of Image Processing is totally related to real time work, which is done by FPGA. Mathematical morphology is a well known image and signal processing technique. However, most morphological tools such MATLAB are not suited for strong real-time constraints. Application of FPGA Coprocessors as a means of delivering hardware IP to software and system engineers is presented. The hardware ...