The recent progress of high level synthesis has illuminated an effective aid for system designers. To keep pace with the development of such an environment, there is a need to consider design for testability (DFT) during the synthesis process. This paper proposes a DFT scheme that can be coordinated with data path synthesis by an interactive trade-off process. The basis of this work is a system...

Testability and design for testability are widely discussed practical issues in software engineering, especially in protocol engineering. A number of basic testability qualities were defined formally and independently from any special system model. In this paper we refine these notions on the one hand by a containment order on experiments and on the other hand by a formal distinction between bo...

We propose a resynthesis method that modifies a given circuit to reduce the number of paths in the circuit and thus improve its path delay fault testability. The resynthesis procedure is based on replacing subcircuits of the given circuit by structures called comparison units. A subcircuit can be replaced by a comparison unit if it implements a function belonging to the class of comparison func...

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This paper illustrates the effect of functional Register Transfer Level (RTL) coding styles on the testability of synthesized gate-level circuits. Thus, the advantage of having a RTL code analyzer to reduce the number of untestable faults, thereby improving the overall testability of a design is presented. In addition, it has been also observed that writing efficient RTL code to improve testabi...

Property testing is a kind of randomized approximation in which one takes a small, random sample of a structure and wishes to determine whether the structure satisfies some property or is far from satisfying the property. We focus on the testability of classes of first-order expressible properties, and in particular, on the classification of prefixvocabulary classes for testability. The main re...

Improving testability during the early stages of the design ow can have several beneets, including signiicantly improved fault coverage, reduced test hardware overheads, and reduced design iteration times. This paper presents an overview of high level design methodologies that consider testability during the early (behavior and architecture) stages of the design ow, and their testability beneet...