We propose a novel idea for the suppression of the dominant mode of the single-mode Fabry-Pérot laser diode (SMFP-LD) to realize all-optical multi-logic functions and a digital adder. The basic principle of the proposed scheme is the power management of input beams to suppress the dominant mode of the SMFP-LD for multi-input injection locking. The proposed principle is explained and implemented...

Due to the trade-off between power, area and performance, various efforts have been done. This work is also based to reduce the power dissipation of the vlsi circuits with the performance upto the acceptable level. The dominant term in a well designed vlsi circuit is the switching power and low-power design thus becomes the task of minimizing this switching power. So, to design a low-power vlsi...

Multi-valued logic gates, which can handle quaternary numbers as inputs, are developed by exploiting the ballistic transport properties of quantum point contacts in series. The principle of a logic gate that finds the minimum of two quaternary number inputs is demonstrated. The device is scalable to allow multiple inputs, which makes it possible to find the minimum of multiple inputs in a singl...

The most important mathematical operation for any computing system is addition. An efficient adder can be of greater assistance in designing of any arithmetic circuits. Quantum-dot Cellular Automata (QCA) is a promising nanotechnology to create electronic circuits for computing devices and suitable candidate for next generation of computing systems. The article presents a modest approach to imp...

Quantum-dot cellular automata (QCA) is a novel nanotechnology that promises smaller size, lower power consumption, with faster speed and is considered as a solution to the scaling problems in complementary metal oxide semiconductor technology. We propose a novel QCA F-shaped XOR gate. The proposed gate is simple in structure and powerful in terms of implementing digital circuits. We implement n...

Received Nov 21, 2017 Revised Jan 29, 2018 Accepted Feb 17, 2018 In the field of Digital signal processing (DSP), the reduction of some logical elements counts is one of the main considerations. To minimize the area, computational delay, and power, the digital form FIR filter is to be implemented. The optimization of the ATP (Area, Time and Power) is achieved by using the efficient multiplicati...

Based on an algorithm derived from the New Chinese Remainder Theorem I, we present three new residue-to-binary converters for the residue number system (2 1 2 2 + 1) designed using 2 -bit or -bit adders with improvements on speed, area, or dynamic range compared with various previous converters. The 2 -bit adder based converter is faster and requires about half the hardware required by previous...

Some arithmetical operations on binary (or 2s complement) numbers performed on Cellular Automata (CA) are presented: a) by implementing on the CA the half-adder functions it is possible to perform a pipelined binary addition of binary number pairs which gives results every two machine-state transitions (after the start-up phase); b) by implementing the full-adder functions on the CA, the sum of...

One of the most important tasks in design and manufacturing of integrated circuits is the testing phase. Distinguishing between faulty and fault free ICs is a difficult task Therefore, simulations are being done for different circuits to identify fault free and faulty circuits. The circuits include analog circuits, digital circuits &mixed signal circuits. Analog circuits like Low pass filter, H...