SRAM Leakage-Power Optimization Framework: a System Level Approach

A novel area-efficient dual replica-bitline delay technique is proposed in this brief to improve process-variation-tolerance of low voltage SRAM application. This strategy suppresses the timing variation by adding one another replica-bitline and introducing novel replica cell which has the same size as conventional. Simulation results in TSMC 65nm LP technology show that more than 32.3% timing ...

Reducing leakage power and improving the reliability of data stored in the memory cells are both becoming challenging as technology scales down. While the smaller threshold voltages causes increased leakage, smaller supply voltages and node capacitances can be a problem for soft errors. This work compares the soft error rates of some recently proposed SRAM leakage optimization approaches. Our r...

A lot of consideration has been given to problems arising due to power dissipation. Different ideas have been proposed by many researchers from the device level to the architectural level and above. However, there is no universal way to avoid tradeoffs between the power, delay and area. This is why; the designers are required to choose appropriate techniques that satisfy application and product...

Die-stacked DRAM caches represent an emerging technology that offers a new level of cache between SRAM caches and main memory. As compared to SRAM, DRAM caches offer high capacity and bandwidth but incur high access latency costs. Therefore, DRAM caches face new design considerations that include the placement and granularity of tag storage in either DRAM or SRAM. The associativity of the cache...

This paper studies the device variability influence on 6T-SRAM cells in a function of the regularity level of their layout. Systematic and random variations have been analyzed when these memory circuits are implemented on a 45 nm technology node. The NBTI aging relevance on these cells has been also studied for two layout topologies and SNM has been seen as the parameter that suffers the highes...

Emerging network applications require packet classification at line speed on multiple header fields. Fast packet classification requires a careful attention to memory resources due to the size and speed limitations in SRAM and DRAM memory used to implement the function. In this paper, we investigate a range of memory architectures that can be used to implement a wide range of packet classificat...

As a follow-up to the May/June Micro Law column on abuse of the standard-setting process, I now turn to Rambus’ version of the previously summarized Secret Squirrel saga. A jury in Richmond, Virginia, found that with the aid of a secret informant (designated Secret Squirrel) inside the Joint Electronic Devices Engineering Council (JEDEC) standard-setting group, Rambus engaged in industrialgrade...

Static random-access memories (SRAMs) exhibit faults that are electrical in nature. Functional and electrical testing are performed to diagnose faulty operation. These tests are usually designed from simple fault models that describe the chip interface behavior without a thorough analysis of the chip layout and technology. However, there are certain technology and layout-related defects that ar...