Presented in this paper is a mathematical basis for power-reduction in VLSI systems. This basis is employed to: 1) derive lower bounds on the power dissipation in digital systems; and 2) unify existing power-reduction techniques under a common framework. The proposed basis is derived from informationtheoretic arguments. In particular, a digital signal processing algorithm is viewed as a process...

The CMOS based dual mode logic gates containing two operating modes: 1) static mode 2) dynamic modes. Features of dual mode logic gates are low power dissipation in static mode and high performance in dynamic mode. This methodology is used to minimize the delay and improve the speed of the logic gates and an additional clocked transistor is used in this methodology. It provides the very high le...

To meet the ever-increasing demand of high performance systems, more and more functions are integrated into single chip by scaling down the size of device. Leakage current is becoming an increasingly important fraction of total power dissipation of integrated circuits. As technology scales leakage current grows exponentially and become and increasingly large component of total power dissipation...

In modern portable devices, the supply voltage is decreased to reduce the power dissipation. However as the supply voltage is scaled down below 0.4V, the normal MOSFET devices cannot be used due to lower ION/ IOFF ratio which will reduce the static power dissipation. Hence for low power applications, Tunnel FET is used as alternatives due to their higher sub threshold swing, extremely low off s...

In the past, the major issue of the VLSI designer were area, cost, performance, and reliability; power consideration was mostly of only inferior importance. But over the last few years power in the circuit is the major problem now days which is being faced by the very large scale integration industries. The power dissipation in any circuit is usually take place by the clocking system which incl...

In this study, it was attempted to design a high-performance single-walled carbon nanotube (SWCNT) bundle interconnects in a full adder. For this purpose, the circuit performance was investigated using simulation in HSPICE software and considering the technology of 32-nm. Next, the effects of geometric parameters including the diameter of a nanotube, distance between nanotubes in a bundle, and ...

This study presents new low-power multiple-valued logic (MVL) circuits for nanoelectronics. These carbon nanotube field effect transistor (FET) (CNTFET)-based MVL circuits are designed based on the unique characteristics of the CNTFET device such as the capability of setting the desired threshold voltages by adopting correct diameters for the nanotubes as well as the same carrier mobility for t...

This paper presents a new approach to an on-chip asynchronous transmission system suitable for next generation asynchronous on-chip networks. It implements multivalued logic to reduce the number of wires and a low-voltage swing for lower dynamic power dissipation. Furthermore, the transmission system described here enjoys fully static design and has zero static power consumption. Two versions o...

Low power consumption and stability in Static Random Access Memories (SRAMs) is essential for embedded multimedia and communication applications. This paper presents a novel design flow for power minimization of nano-CMOS SRAMs, while maintaining their stability. A 32 nm High-κ/Metal-Gate SRAM has been used as example circuit. The baseline SRAM circuit is subjected to power minimization using a...

Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as meshes and crosslinks, are employed to reduce skew and also to mitigate skew variations. These networks, however, increase the dissipated power while consuming significant metal resources. Several methods have been pro...