Increased leakage current and device variability are the major challenges with CMOS technology scaling. Since Static Random Accessed Memory (SRAM) is often the largest component in the embedded digital systems or System-on-Chip (SoC), it is more vulnerable to those challenges. To effectively reduce SRAM leakage and/or active power, supply voltage (VDD) is often scaled down during standby and/or...

The binary values processed and stored at the intermediary stages of an algorithm are often highly correlated. Motivated in part by this observation and the ever-increasing challenge of power density for Integrated Circuit (IC) systems, a novel reconfigurable memory framework is proposed in this thesis which builds upon traditional low power techniques such as voltage scaling in order to achiev...

Outline zIntroduction zRelated Work zSleepy stack zSleepy stack logic circuits zSleepy stack SRAM zLow-power pipelined cache (LPPC) zSleepy stack pipelined SRAM zConclusion

We propose a novel substrate-bias control scheme for an FD-SOI SRAM that suppresses inter-die variability. The proposed circuits detect inter-die threshold-voltage variation automatically, and then maximize read/write margins of memory cells to supply the substrate bias. We confirmed that a 486-kb 6T SRAM operates at 0.42 V, in which an FS corner can be compared as much as 0.14 V or more. key w...

A closed loop self-tuning 256kb 6T SRAM with 0.38V-1.2V extended operating range using combined read and write assists and canary-based VMIN tracking is presented. 337X and 4.3X power reductions are achieved using multiple assists and VMIN tracking, respectively; combining both saves 1444X in active power and 12.4X in leakage at the 0.38V. Keywords—self-tuning SRAM; combined assists; canary SRA...

This paper demonstrates an asynchronous implementation of a FIFO based on 4 phase bundled data protocol, interfaced with an SRAM. Both FIFO and SRAM are modeled using VHDL and use the asynchronous handshaking principles for communication. Timing and power analysis for the design is also presented. The synthesis, simulation and analysis is done with the help of Xilinx ISE version 9.1i Keywords— ...

Considerable attention has been paid to the design of low-power, high-performance SRAMs (Static Random Access Memories) since they are a critical component in both hand-held devices and high-performance processors. A key in improving the performance of the system is to use an optimum sized SRAM. In this thesis, an SRAM compiler has been developed for the automatic layout of memory elements in t...

— Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicron regime. As a result, reducing the subthreshold and tunneling gate leakage currents has become one of the most important criteria in the design of VLSI circuits. This paper presents a method based on dual-V t and dual-T ox assignment to reduce the total leakage power...

In the past decades CMOS IC technologies have been constantly scaled down and at present they aggressively entered in the nanometer regime. Amongst the wide-ranging variety of circuit applications, integrated memories especially the SRAM cell layout has been significantly reduced. As it is very well know the reduction of size of CMOS involves an increase in physical parameters variation, this i...

Secure storage of cryptographic keys in hardware is an essential building block for high security applications. It has been demonstrated that Physically Unclonable Functions (PUFs) based on uninitialized SRAM are an effective way to securely store a key based on the unique physical characteristics of an Integrated Circuit (IC). The startup state of an SRAM memory is unpredictable but not truly ...