This paper presents a novel sigma-delta modulator architecture dedicated to very low-power applications wherein third-order noise shaping is achieved with very modest constraints on the analog part. The architecture is based on an enhanced MASH structure where the feedback of every loop is the sum of its output and of the output of the following loops. The analytical model of the architecture i...

A reduced complexity digital multi-stage noise shaping (MASH) delta–sigma modulator for fractional-N frequency synthesizer applications is proposed. A long word is used for the first modulator in a MASH structure; the sequence length is maximized by setting the least significant bit of the input to “1;” shorter words are used in subsequent stages. Experimental results confirm simulations.

In wide band communication systems, low power and high speed ADCs forms the main building blocks. These ADCs are commonly seen in the front end of the radio frequency receivers. Comparators are used in these ADCs. A CMOS Comparator design, based on amplifier-push pull inverter circuit is elaborated in this paper, which is intended to be used as the 1-bit ADC required for the implementation of a...

An eighth-order switched-current bandpass delta-sigma modulator is described. Simulations indicate that our 1.2pm CMOS implementation will achieve a S N R of 90dB in the band 10 MHzk150 KHz when clocked at 40 MHz. The modulator makes use of a switched-current resonator based on the N-path technique and the resonator employs regulated-cascode current-copiers to simultaneously achieve high speed ...

The paper proposes a novel structure for a MASH digital delta-sigma modulator (DDSM) in order to achieve a long sequence length. The expression for the sequence length is derived. The condition to produce the maximum sequence length is also stated. It is proved that the modulator output only depends on the structure of the first-order error feedback modulator (EFM1) which is the first stage of ...

The paper details on-chip inductor optimization for a reconfigurable continuous-time delta-sigma (Δ-Σ) modulator based radio-frequency analog-to-digital converter. Inductor optimisation enables the Δ-Σ modulator with Q enhanced LC tank circuits employing a single high Q-factor on-chip inductor and lesser quantizer levels thereby reducing the circuit complexity for excess loop delay, power dissi...

A methodology for the design of Continuous-Time (CT) Sigma-Delta (Σ∆) modulators with VCO-based quantizer is proposed. The coefficients of the CT Σ∆ modulator are accurately calculated such that the noise transfer function of the modulator is exactly the same as a Discrete-Time (DT) Σ∆ modulator of the same order. Several design examples for different modulator orders and feedback DAC signal sh...

In a previous study [1], we proposed an adaptive sigma delta modulator with improved dynamic range. The modulator adapts the step size of the quantizer from estimates of the quantizer input instead of the modulator input. In this study, we conduct an error variance analysis of the new modulator and derive expression for the SNR. The derived expression shows that the SNR is independent of the in...