In this paper we propose a digital background adaptive calibration technique for correcting offset and gain mismatches in multi-path sigma-delta (ZA) modulators. The proposed technique allows us to cancel the spurious tones introduced by offset and gain mismatches among the paths only by processing the digital output, without interfering with the operation of the modulator. This solution is als...

This paper presents a 2-GHz tunable direct sampling receiver with 40-GHz sampling clock and on-chip PLL, fabricated in a production 130-nm SiGe BiCMOS process. The measured SFDR and SNDR are 59 dB and 59.84 dB, respectively, over a bandwidth of 60 MHz, and the effective number of bits (ENOB) equals 9.65. Compared to the case where an external low-noise 40-GHz clock was used, no SNDR degradation...

This research presents the review of Analog to Digital Convertor (ADC). For ADC there are mainly four different methods, Flash ADC, Pipelined ADC, Successive Approximation ADC, and Sigma Delta ADC. The Flash ADC is the Fast ADC. For Designing the ADC, the parameters important are Static and Dynamic. In static parameters Differential Non Linearity Error (DNLE), Integral Non Linearity Error (INLE...

A 9-bit 11GS/s current-steering (CS) digital-to-analog converter (DAC) is designed in 28nm FDSOI. The DAC uses two-times interleaving to suppress the effects of the main error mechanisms of CS DACs while its clock timing can be tuned by the back gates bias voltage of the multiplexer transistors. The DAC achieves higher than 50dB SFDR and less than -50dBc IM3 over Nyquist at a sampling rate of 1...

This paper presents a 12-bit 2.32 GS/s time-interleaved pipelined/successive-approximation register (SAR) hybrid analog-to-digital converter (ADC) implemented in 28 nm CMOS. To achieve high-linearity at several GS/s, pseudo-differential push-pull input buffer with floating-body technique is proposed. A pipelined/SAR architecture dual-channel sampling multiplying digital-to-analog (MDAC) and one...

Direct digital frequency synthesizers (DDSs) are of interest in modern digital communication systems and high-precision function generation. Wide frequency synthesis range, agile and continuous phase frequency switching, fine frequency resolution, and the ability to synthesize arbitrary waveforms as well as sinewaves are some of the important advantages of this family of frequency synthesizers....

A 10 bit current steering CMOS digital-to-analog converter (DAC) is designed, with optimized performance for frequency domain applications. To get the best of both binary-weighted and thermometer-coded architectures, most current-steering D/A converters are implemented using a segmented architecture. Segmentation is chosen to reduce the total area occupied by the DAC. The optimum segmentation f...

In this paper, a high-speed low-power SAR ADC is designed. prototype, an improved switching scheme combined with the optimized attenuation capacitor architecture proposed, showing more power efficiency and suitable for data converters. Meanwhile, synchronous timing strategy employed, achieving flexible time allocation of DAC settling comparison in each bit-cycle. addition, two-stage non-tail-cu...