Many of today's high level parallel languages support dynamic, ne-grained parallelism. These languages allow the user to expose all the parallelism in the program, which is typically of a much higher degree than the number of processors. Hence an eecient scheduling algorithm is required to assign computations to processors at runtime. Besides having low overheads and good load balancing, it is ...

A novel power-efficient IC test scheme is proposed, containing parallel test application (PTA) architecture and its procedure. PTA parallelizes the stimuli assignments and the vectors can be observed immediately once applied, which assures the shift safety timely and hence only logic test is required. The procedure contains two phases for each pattern. In shift phase, each clock chain is activa...

In this paper, the authors propose a new structured multisignature scheme that considers the signing order among co-signers. The proposed scheme can resolve signing structures of serial, parallel, and the mix of them. Moreover, the size and the verification of a structured multisignature is the same as those of an individual signature generated by any co-signer. Arithmetically, the proposed sch...

This article presents a new parallel method for implicit surface voxelization the determination of which cells of a regular grid in 3-space intersect the zero-set of an implicit function. The serial version of the method uses interval arithmetic to rapidly prune regions of space where the surface does not lie, and a novel octree generation/storage scheme for recording the voxels the surface mee...

The Polynomial basis (PB) representation offers efficient hardware realizations of GF (2) multipliers. Bit-level serial multiplication over GF (2) trades-off the computational latency for lower silicon area, and hence, is favored in resource constrained applications. In such area critical applications, extra clock cycles might take place to read the inputs of the multiplication if the data-path...

The paper is aimed at a new system for generation of suitable BIST (Built-in Self-Test) blocks for effective testing of multiple memories integrated in a SoC (System on Chip). Incoming technologies, chip complexity and increasing clock frequencies give new challenges for testing huge number of embedded SoC memories. SoCs have to be tested after their manufacturing and always during their life-t...

Three parallel algorithms for solving the 3D problem with nonlocal boundary condition are considered. The forward and backward Euler finite-difference schemes, and LOD scheme are typical representatives of three general classes of parallel algorithms used to solve multidimensional parabolic initial-boundary value problems. All algorithms are modified to take into account additional nonlocal bou...

Genetic Programming (GP) was used to generate robot control programs for an obstacle avoidance task [1]. The task was to control an autonomous mobile robot from a starting point to a target point in a simulated environment. The environment was filled with the obstacles which had several geometrical shapes. In order to improve the robustness of the program, each program was evaluated under many ...

Monte Carlo (MC) methods have proved to be flexible, robust and very useful techniques in computational finance. Several studies have investigated ways to achieve greater efficiency of such methods for serial computers. In this paper, we concentrate on the parallelization potentials of the MC methods. While MC is generally thought to be “embarrassingly parallel”, the results eventually depend o...

When a loop in a sequential program is parallelized, it is normally guaranteed that all ow dependencies and anti-dependencies are respected so that the result of parallel execution is always the same as sequential execution. In some cases, however, the algorithm implemented by the loop allows the iterations to be executed in a di erent sequential order than the one speci ed in the program. This...