An implementation of a design for testability model for sequential circuits is presented. The jlip-jlops in a sequential circuit are partitioned to reduce the number of cycles and the path lengths in each partition, thereby reducing the complezity of test generation. The implementation includes a Podem-based test generator. Preliminary results using the Contest sequential test generator are pre...

We present a new pattern generation approach for deterministic built-in self testing (BIST) of sequential circuits. Our approach is based on precomputed test sequences, and is especially suited to sequential circuits that contain a large number of flip-flops but relatively few controllable primary inputs. Such circuits, often encountered as embedded cores and as filters for digital signal proce...

We present an efficient register-transfer level automatic test pattern generation (ATPG) algorithm. First, our ATPG generates a series of sequential justification and propagation paths for each RTL primitive via a deterministic branch-and-bound search process, called a test environment. Then the precomputed test vectors for the RTL primitives are plugged into the generated test environments to ...

This paper focuses on testing sequential circuits using a simple form of signature analysis as a compaction technique. More specifically, the paper describes a systematic methodology for calculating the probability of aliasing when a randomly generated test input vector sequence is applied to a given finite state machine (FSM) and the final FSM output is used to verify the functionality of the ...

1. Introduction Two different ideologies can be considered for handling an error detected in a circuit concurrently with its functioning. The first ideology is based on the immediate marking of the circuit as erroneous when an error is detected. An alternative ideology concentrates on increasing the survivability of the circuit, which means, "to give a chance" to the circuit to continue to work...

Motor circuits in the spinal cord integrate information from various sensory and descending pathways to control appropriate motor behavior. Recent work has revealed that target-derived retrograde signaling mechanisms act to influence sequential assembly of motor circuits through combinatorial action of genetic and experience-driven programs. These parallel activities imprint somatotopic informa...

Complex VLSI circuits impose constraints on a test generator which are very diicult to handle using deterministic algorithms. Thus, a major goal in developing a new test generator is to have the capability of handling constraints, but without sacriicing the performance and eeectiveness of deterministic approaches. In this paper, we describe a hybrid sequential circuit test generator which combi...

Testing of Sequential circuits can be done by two test vectors (all 1’s and all 0’s) if the circuits were based on the conservative logic. The circuit is made to be tested by designing the circuit with the help of Reversible logic gates. Toffoli gate is used as reversible gate in this paper. Sequential circuits such as latches, flip flops are designed with the help of conservative logic reversi...

We propose a formulation of the sensitization constraints that must be satisfied by all true paths in a sequential circuit and suggest a number of approximations to these constraints aimed at simplifying their computation while capturing their essential dependencies. Using one of these approximations we show how an existing combinational timing analysis tool, can be easily augmented to identify...

The paper proposes a Design-for-Testability (DfT) technique of Built-In Self-Test (BIST) for sequential circuits. The technique is based on making the status signals entering the control part controllable during the test mode to force the device under test to traverse all the branches in the FSM state transition graph. Extra outputs are added to the circuit under test in order to observe the va...