We propose a new approach to parallelizing fault simulation in which the test set is partitioned among the available processors. The approach can be used for any of the sequential circuit fault simulation algorithms commonly used, and it can be implemented on various diierent parallel architectures. This approach for the rst time overcomes the limitations of serial logic simulation. In addition...

Realizing a sequential machine with shift registers is an attractive approach to the design for testability. It requires little extra circuit for scan and since feed-backs are always to the rst ip-op of a shift register test generation is expected to be easier than that for circuits with unstructured feedbacks. Though the shift register realization of sequential machines was studied by several ...

In this article we present a strategy how to estimate the signal probabilities for synchronous sequential circuits. For each line in the circuit an OBDDs is constructed only once. Using this OBDD the signal probabilities in every succeeding time frame is computed. We investigated a large set of the ISCAS'89 benchmark circuits, showing that the proposed strategy estimates 75% of all signals cons...

 This paper presents a BDD-based approach to perform logic partitioning for sequential circuits. We use a sequential machine to model a circuit and represent the machine by its transition relation. A heuristic algorithm based on the BDD representation of the transition relation is proposed to partition the sequential machine with minimum number of input/output pins. Using BDDs and their operat...

Abstract The development of technology in the industrial world 4.0 is very fast, particular it can be seen rapidly growing remote control system, use applications via network increasing, and so on. Remote such as Arduino with an internet that used a tool to provide information receive industry save terms time, employees other operational costs. This paper aims utilize controlling electric motor...

A novel technique called reverse circuit execution is presented as an efficient approach towards integrated parallel execution of multiple sequential circuit simulators. The unique aspect of this approach is that it does not require source code modifications to either simulation engines or circuit models, and hence holds appeal in situations where parallelism is desirable but without access to ...

Formal hardware verification ranges from proving that two combinational circuits compute the same functions to the much more ambitious task of proving that a sequential circuit obeys some abstract property expressed in temporal logic. In tracing the history of work in this area, we find a few efforts in the 1970s and 1980s, with a big increase in verification capabilities the late 1980s up thro...