.............................................................................................................................. ii Acknowledgements............................................................................................................ iii Table of

A reconfigurable wavefront array rDPA (reconfigurable datapath architecture) for evaluation of any arithmetic and logic expression is presented. Introducing a global I/O bus to the array simplifies the use as a coprocessor in a single bus oriented processor system. Fine grained parallelism is achieved using simple reconfigurable processing elements which are called datapath units (DPUs). The wo...

This paper presents the following algorithms to compute the sum of n d-bit integers on reconfigurable parallel computation models: (1) a constant-time algorithm on a reconfigurable mesh of the bit model of size &log(‘(‘)) n x dfi, (2) an O(log*n)-time algorithm on a reconfigurable mesh of the bit model of size dm x ddm, (3) an O(logd + log*n)-time algorithm on a reconfigurable mesh of the word ...

While fine-grain, reconfigurable devices have been available for years, they are mostly used in a fixed functionality, “asic-replacement” manner. To exploit opportunities for flexible and adaptable run-time exploitation of fine grain reconfigurable resources (as implemented currently in dynamic, partial reconfiguration), better tool support is needed. The FASTER project aims to provide a method...

With the increasing requirements of more flexibility and higher performance in embedded systems design, the concept of reconfigurable computing has become more attractive. Especially, there have been many coarse-grained reconfigurable array architectures proposed and/or commercialized. However, the existing reconfigurable array architectures have been designed without the concept of application...

Recently reconfigurable devices such as FPGA have improved performance (gate speed and the number of gates) and reconfiguration time. Today , a reconfigurable device can integrate a large-scale processor and complex hard-wired logic. System designers found that they need a high-performance processor for their reconfigurable device based systems. To improve processor performance , a multithreade...

Modern reconfigurable computing systems feature powerful hybrid architectures with multiple microprocessor cores, large reconfigurable logic arrays and distributed memory hierarchies. Mapping applications to these complex systems requires a representation that allows both hardware and software synthesis. Additionally, this representation must enable optimizations that exploit fine and coarse gr...

Reconfigurable instruction set processors have the capability to adapt their instruction sets to the application being executed through a reconfiguration in their hardware. Through this adaptation, they are expected to achieve a great improvement in performance compared to fixed instruction set processors. In this paper, we discuss the different hardware aspects that have to be considered durin...

In this paper we describe a peer-to-peer interface between processor cores and reconfigurable fabrics. The main advantage of the peer-to-peer model is that it greatly expands the scope of application for reconfigurable computing and hence its potential benefits. The primary extension in our model is that “code” on the reconfigurable hardware unit is allowed to invoke routines both on the reconf...