Memories are a core part of most of the electronic systems. Performance in terms of speed and power dissipation is the major areas of concern in today’s memory technology. In this paper SRAM cells based on 6T, 7T, 8T, and 9T configurations are compared on the basis of performance for read and write operations. Studied results show that the power dissipation in 7T SRAM cell is least among other ...

Conventional delay-insensitive (DI) data encodings require 2N+1 wires for transferring N-bit. To reduce complexity and power dissipation of wires in designing a large scaled chip, a DI data transfer mechanism based on current-mode multiple valued logic (CMMVL), where N-bit data transfer can be performed with only N+1 wires, is proposed. The effectiveness of the proposed data transfer mechanism ...

sumption in active mode as a tradeoff to increased performance, but any power consumed when the system is idle is a complete waste and ideally should be avoided by turning the system off. A typical current system is so complex that parts of it will likely be inactive even during active periods, and they can be turned off to reduce power with no impact on performance. The introduction of finer-g...

This paper reviews the three Conditional internal activity Techniques for high performance flip-flops namely Conditional Capture, Conditional Precharge and Conditional Discharge techniques. These techniques are reviewed in terms of power and delay and classified based on how to prevent or reduce the internal switching activity. Application of the Conditional techniques results in improvement of...

In this paper, footless domino logic buffer circuit is proposed. It minimizes redundant switching at the dynamic and the output nodes. This circuit passes propagation of precharge pulse to the dynamic node and avoids precharge pulse to the output node which saves power consumption. Simulation is done using 0. 18μm CMOS technology. We have calculated the power consumption, delay and power delay ...

   This paper presents a novel design of quaternary logic gates using graphene nanoribbon field effect transistors (GNRFETs). GNRFETs are the alternative devices for digital circuit design due to their superior carrier-transport properties and potential for large-scale processing. In addition, Multiple-valued logic (MVL) is a promising alternative to the conventional binary logic design. Sa...

This paper presents the design of high-speed full adder circuits using a new CMOS mixed mode logic family. The objective of this work is to present a new full adder design circuits combined with current mode circuit in one unit to implement a full adder cell. This paper also discusses a highspeed hybrid majority function based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure ...

Design of a new sense amplifier-based flip-flop (SAFF) using GDI Technique and performance comparison of proposed SAFF with existing conventional SAFF with CMOS-NAND latch SAFF and SAFF with CMOS Symmetric latch is presented in this paper. It was found that the main drawback of existing SAFF’s is the cross-coupled set-reset (SR) latch in the output stage. The new flip-flop uses a new output sta...

This paper presents a novel approach to design robust source coupled logic for implementing ultra low power circuits. In this paper, we proposed two different source coupled logic structures and analyzed the performance of these structures with STSCL. The first design we used DTPMOS as load device and analyses the performance of DTSCL Logic with previous source coupled logic for ultra low power...

A novel and robust scheme for radix-4 Booth scheme implemented in Carbon Nanotube Field-Effect Transistor (CNTFET) technology has been presented in this paper. The main advantage of the proposed scheme is its improved speed performance compared with previous designs. With the help of modifications applied to the encoder section using Pass Transistor Logic (PTL), the corresponding capacitances o...