This paper describes the development and presents test results of a thin-film, high-current density, iridium oxide (IrOx) microelectrode for neuromuscular stimulation. The electrode is made of a silicon substrate with polysilicon lines as the interconnect and Irox as the electrode material. The polysilicon lines are protected from body fluids by silicon dioxide and silicon nitride. The electrod...

Several recent studies have underlined the need for trusted information displays in current and future personal devices. On the other hand, the display market is more and more dominated by low-cost flatpanel structures, driven by Thin-Film Transistor (TFT) circuits. Further, the quality of TFT-based electronics is constantly improving, allowing the fabrication of complicated electronic circuits...

A silicon micromachining method has been developed to fabricate on-chip high-performance suspended spiral inductors. The spiral structure of an inductor was formed with polysilicon and was suspended over a 30m-deep cavity in the silicon substrate beneath. Copper (Cu) was electrolessly plated onto the polysilicon spiral to achieve low resistance. The Cu plating process also metallized the inner ...

In order to characterize the fatigue behaviour and determine the fracture energy of polysilicon used in micro-systems, an on-chip testing device has been designed and fabricated. The experimental set-up is able to continuously measure the elastic stiffness decrease and therefore to evidence fatigue of polysilicon 15-μm thick films and to allow for the introduction of a sharp crack at the notch ...

In silicon surface micromachining, anhydrous HF GPE process was verified as a very effective method for the dry release of microstructures. The developed gas-phase etching (GPE) process with anhydrous hydrogen fluoride (HF) gas and alcoholic vapor such as methanol, isopropyl alcohol (IPA) was characterized and its selective etching properties were discussed. The structural layers are P-doped mu...

Deposition process for thin insulator used in polysilicon gate dielectric of thin film transistors are optimized. Silane and N2O plasma are used to form SiO2 layers at temperatures below 150 ºC. The deposition conditions as well as system operating parameters such as pressure, temperature, gas flow ratios, total flow rate and plasma power are also studied and their effects are discussed.  The p...

In this paper, we propose a novel design analysis for a Junctionless Double Gate Vertical MOSFET (JLVMOS) with metal gate electrode and HfO2, for which the simulations have been performed using TCAD (ATLAS), The simulated results exhibits significant improvements in comparison to conventional JLVMOS device with a polysilicon gate electrode and ITRS values for different node technology . In plac...

New techniques and procedures are described that enable one to measure the mechanical properties of polysilicon films that are 3.5 μm thick. Polysilicon is deposited onto a silicon substrate which is then etched away to leave a tensile specimen in the middle of the die. The grip ends of the structure are glued to the grips of a linear air bearing attached to a piezoelectrically actuated loading...

In this work we study the feasibility to obtain the smallest CMOS-NEMS resonator using a sub-100 nm CMOS technology. The NEMS resonators are defined in a top-down approach using the available layers of the 65 nm CMOS technology from ST Microelectronics. A combination of dry and wet etching is developed in order to release the NEMS in an in-house post-CMOS process. Two different NEMS resonators ...