The paper introduces a new approach based on dual residue system to compute Montgomery multiplication. The novelty of this proposal is that we import an extra Montgomery residue system with new transformation constant beside the normal one. In this way, one of the multiplicand can be divided into two parts and both higher and lower parts are calculated in parallel to speed up computation. Then ...

At Crypto 2009 [1], Bernstein initiated an optimization of Karatsuba formula for binary polynomial multiplication by reorganizing the computations in the reconstruction part of two recursions of the formula. This approach was generalized in [10] to an arbitrary number of recursions resulting in the best known bit parallel multiplier based on Karatsuba formula. In this paper we extend this appro...

This paper presents a new architecture style for the design of a parallel floating point multiplier. The proposed architecture is a synergy of trees and arrays. Architectural models were designed to implement the 53-bit mantissa path of the IEEE standard 754 for floating point multiplication, and tested for functionality in Verilog. The design, which was done in dual-rail domino, was simulated ...

Matrix multiplication is a computationally-intensive and fundamental matrix operation in many algorithms used in scientific computations. It serves as the basic building block for signal, image processing, graphics and robotic applications. To improve the performance of these applications, a high performance matrix multiplier is required. Traditionally, matrix multiplication operation is either...

This paper describes the work done towards design and implementation of multiplier modules using high speed architectures based on the concept of Vedic Mathematics. Unlike other Vedic multipliers where entire architecture is based on generating partial products in parallel and adding them, here the partial products for top level entity are adjusted using concatenation operation and are added us...

This paper presents a merged multiplyaccumulate (MAC) hardware that is based on the modified Booth algorithm. The carry-save method is used in the Booth encoder, the Booth multiplier, and the accumulator sections to guarantee the fastest possible. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Also, the proposed ...

This paper presents a merged multiplyaccumulate (MAC) hardware that is based on the modified Booth algorithm. The carry-save method is used in the Booth encoder, the Booth multiplier, and the accumulator sections to guarantee the fastest possible. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Also, the proposed ...

One of the well-known problems in evolutionary search for solving optimization problem is the premature convergence. The general constrained optimization techniques such as hybrid evolutionary programming, two{phase evolutionary programming, and Evolian algorithms are not safe from the same problem in the rst phase. To overcome this problem, we apply the sharing function to the Evolian algorith...

(ii) Use of multiplier blocks can drastically change the complexity relations between different structures. Despite using almost twice the wordlength, and many more coefficients (corresponding to having almost 2.5 times the complexity using the C, measure), the direct forms require similar numbers of adders to the waveform. Similarly, but less dramatically, the cascade and parallel forms are si...

We present a mixed-signal distributed VLSI architecture for massively parallel array processing, with fine-grain embedded memory. The three-transistor processing element in the array combines a charge injection device (CID) binary multiplier and analog accumulator with embedded dynamic random-access memory (DRAM). A prototype 512 128 vector-matrix multiplier on a single 3 mm 3 mm chip fabricate...