A systolic algorithm is described for generating, in lexicographically ascending order, all combinations of rn o$ects chosen from an arbitrary set of n elements. The algorithm is designed to be executed on a linear array of zn processors, each having consta.nt size memory (except processor rn, which has O(n) memory), and each being responsible fot producing one element of a given combination. T...

An abandoned fetus with suspicious skin injuries was found dead, lying on the grass of a garden, near a private house. Suspecting infanticide, the prosecutor ordered a medico-legal autopsy. The cause of death was identified as a congenital malformation of the central nervous system such as hydranencephaly, and infanticide was excluded.

Recently researchers have shown interest in integrating Reconfigurable logic into conventional processors as a Reconfigurable Function Unit (RFU). A context-full RFU supports holding intermediate results inside itself, which eliminates some data movement overheads and has some other benefits. Most contemporary processors support out-of-order execution and speculation. When a context-full RFU is...

The adaptive software paradigm supports the definition of software systems that are continuously adapted at run-time. An adaptation activates multiple features in the system, according to the current execution context (e.g., CPU consumption, available bandwidth). However, the underlying approaches used to implement adaptation are ordered, i.e., the order in which a set of features are turned on...

Several studies have demonstrated that out-of-order execution processors may not be the most adequate organization for wide issue processors due to the increasing penalties that wire delays will cause in the issue logic. The main target of out-of-order execution is to hide functional unit latencies and memory latency. However, the former can be quite effectively handled at compile time and this...

We consider the problem of evaluating a function f(x, y) (x E sm, y E Rn) using two processors P1 and P2, assuming that processor P1 (respectively, P2) has access to input z (respectively, y) and the functional form of f. We establish a new general lower bound on the communication complexity (i.e., the minimum number of real-valued messages that have to be exchanged). We then apply our result t...

An important design issue of SMT processors is to find proper sharing strategies of resources among threads. This paper proposes a ROB sharing strategy, called paired ROB, that considers the fact that task parallelism is not always available to fully utilize resources of multithreaded processors. To this aim, an evaluation methodology is proposed and used for the experiments, which analyzes per...

An increasing cache latency in next-generation processors incurs profound performance impacts in spite of advanced out-of-order execution techniques. One way to circumvent this cache latency problem is to predict load values at the onset of pipeline execution by exploiting either the load value locality or the address correlation of stores and loads. In this paper, we describe a new load value ...

This work has been inspired by problems addressed in the field of computer security, where the attacking of, e.g., password systems is an important issue. In [2] Lundin et al. discuss measures related to the number of guesses or attemts a supposed attacker needs for revealing information. Similar problems are considered in [1], [3] and [4]. In this presentation numerical approaches are discusse...

Decoupled architectures have previously been investigated in the context of high performance scientific computing. For general purpose computing, however, superscalar processors have proven to be flexible in providing high performance across a wide range of applications. To achieve this goal, these architectures have incorporated enormous amounts of complexity to obtain modest performance impro...