Design of a high performance and high-density multiplier is presented. This multiplier is constructed by using the Wallace tree structure with pipelining. A fast carry select adder is used for the final two-operand adder. It is shown that the time delay for the entire multiplier is O(log(n)). The design is particularly carried out for a 32-bit multiplier with two sections of pipelining, to bala...

We present a new low-complexity bit-parallel canonical basis multiplier for the field GF(2 m ) generated by an all-onepolynomial. The proposed canonical basis multiplier requires m 2 1 XOR gates and m 2 AND gates. We also extend this canonical basis multiplier to obtain a new bit-parallel normal basis multiplier.

In the recent year growth of the portable electronics is forcing the designers to optimize the existing design for better performance. Multiplication is the most commonly used arithmetic operation in various applications like, DSP processor, math processor and in various scientific applications. In this paper a low power bypassing -based multiplier design is present, in which reduction in power...

Multipliers play a vital role in many cryptographic applications like elliptic curve cryptography, RSA and other algorithms. The direct truncation of least significant part of the product leads to large error in the resultant product when fixed width output is the requirement. This paper proposes a truncation error minimizing logic which greatly reduces truncation error. Truncation error minimi...

This study presents a novel sequential Type-I optimal normal basis multiplier in GF(2) with a regular structure. The proposed multiplier has a slightly higher space complexity than the Reyhani-Masoleh-Hasan’s (RMH) multiplier, but is 27% faster than the RMH multiplier. Furthermore, the proposed multiplier is highly regular, modular, expandable and well-suited to VLSI implementation. A new norma...

| We present a new low-complexity bit-parallel canonical basis multiplier for the eld GF2 m generated by a n all-one-polynomial. The proposed canon-ical basis multiplier requires m 2 , 1 XOR gates and m 2 AND gates. We also extend this canonical basis multiplier to obtain a new bit-parallel normal basis multiplier.

The accuracy of the multiplication depends on the precision of the multiplier. The variable precision floating point multiplier will have more accuracy when compared with the fixed precision multiplier. In this paper a variable precision floating point multiplier is considered. An effective BIST test pattern generator for variable precision floating point multiplier is proposed. A BIST TPG cons...