This paper includes the designing of 16Bit RISC processor and modeling of its components using VHDL. The implementation strategies have been borrowed from most popular MIPS architecture up to certain extent. The instruction set adopted here is extremely simple that gives an insight into the kind of hardware which should be able to execute the set of instructions properly. Along with sequential ...

The problem of scheduling a set of tasks to a set of processors can be divided into two categories: job scheduling and scheduling and mapping. In the former category, independent jobs are to be scheduled among the processors of a distributed computing system to optimize overall system performance [1][2]. In contrast, the scheduling and mapping problem requires the allocation of multiple interac...

We study shared multi-processor scheduling problem where each job can be executed on its private processor and simultaneously on one of many processors shared by all jobs in order to reduce the job’s completion time due to processing time overlap. The total weighted overlap of all jobs is to be maximized. The problem models subcontracting scheduling in supply chains and divisible load schedulin...

An adaptive low-complexity space-time reduced-rank processor is proposed for interference suppression in asynchronous DS code division multiple access (CDMA) systems based on a diversity-combined decimation and interpolation method. The novel design approach for the processor employs an iterative procedure to jointly optimise the interpolation, decimation and estimation tasks for reduced-rank p...