This paper describes a transistor sizing methodology for both analog and digital CMOS circuits. Various techniques are used for power optimization in CMOS VLSI circuits. Transistor sizing is one of the important techniques for the determination of circuit performance. The aim of the power optimization is to minimize the power and power-delay product or the energy consumption of the circuit. Thu...

In this paper, a novel low power pulsed flip-flop (PFF) using self-controllable pass transistor logic is presented. The pulse generation logic comprising of two transistor AND gate is used in the critical path of the design for improved speed and reduced complexity. In the D to Q path inverter is removed and the transistor is replaced with pass transistor logic. The pass transistor is driven by...

We propose and demonstrate both a binary and ternary adder circuit based on a resonant tunneling diode (RTD) and a bipolar transistor. The basic switching cell consists of an RTD in series with the base of a bipolar transistor. The RTD is used to set a threshold voltage for the switching of the transistor.

In this paper we consider transistor sizing to reduce crosstalk. First, crosstalk noise dependency on wire width, wire spacing, driver and receiver sizes are discussed, and validated by experiments. Then transistor sizing for timing and noise is discussed and solved using optimization techniques. Experimental results suggest that crosstalk violations can be removed by transistor sizing with ver...

A system for the generation of short electrical pulses based on the minority carrier charge storage and the step recovery effect of bipolar transistors is presented. Electrical pulses of about 90 ps up to 800 ps duration are generated with a maximum amplitude of approximately 7 V at 50. The bipolar transistor is driven into saturation and the base-collector and base-emitter junctions become fo...

In this paper, Adomian Decomposition Method (ADM) is used to study the linear time-invariant transistor circuit. The results obtained using Adomian Decomposition Method and the methods taken from the literature [5] were compared with the exact solutions of the linear time-invariant transistor circuit. It is found that the solution obtained using the Adomian Decomposition Method is closer to the...

We used an ensemble Monte Carlo simulator to study both the dc and transient behavior of a double gate silicon-on-insulator transistor sDGSOId operated as a velocity modulation transistor sVMTd and as a conventional field effect transistor sFETd. Operated as a VMT, the DGSOI transistor provides switching times shorter than 1 ps regardless of the channel length, with a significant current modula...

Partition noise is closely related to reset noise and has been observed in detection nodes of reset transistor architecture in image sensors. This work presents the analysis of partition noise based on an improved technique for estimation of charge distribution in the transistor channel at any given time instant. We incorporate the transistor turn off transients by taking into account both drif...