In this paper a low power SRAM design is presented. Existing SRAM architectures used in SGSThomson were studied to explore the possibilities in bringing down power dissipation in various blocks. A Divided word line (DWL) scheme was implemented. Particular emphasis was put to reduce power consumption in decoders. A new critical path model was introduced for schematic simulation. This lowered the...

The release of a CMOS low power library by the Infopad group at UC Berkeley gave engineers the ability to develop low power circuits with standard cells in Magic with minimum geometry layouts [1]. We describe a process that translates this low power standard cell library from Magic into the Mentor Graphics (MGC) environment. Using the Design Kit Example (DKE), we describe the steps to build a c...

Reference design for radio part is OKI’s ML7050LA [2] single chip RF having for example following blocks integrated: Low noise amplifier (LNA), power amplifier (PA), image rejection mixer (IMR). Block diagram of ML7050LA is in Figure 1. By assuming to use 3 V supply voltage Tx power dissipation is 102mW and Rx power dissipation is 165mW. Abstract—Wireless sensor networks have several challenges...

The explosive growth of battery operated devices has made low-power design a priority in recent years. Moreover, embedded SRAM units have become an important block in modern SoCs. The increasing number of transistor count in the SRAM units and the surging leakage current of the MOS transistors in the scaled technologies have made the SRAM unit a power hungry block from both dynamic and static p...

Ubiquitous computing is a next generation information technology where computers and communications will be scaled further, merged together, and materialized in consumer applications. Computers will be invisible behind broadband networks as servers, while terminals will come closer to us as wearable/implantable devices, more friendly devices with sophisticated human-computer-interactions. IC ch...

The aim of this document is to provide the reader with an overview of low-power digital design trends. Several research publications and books have been studied by the author and the knowledge gained has been compiled into this report. Low-power techniques adopted at different levels of the design process are presented and industrial application examples are given.

Digital signal processing is an area of science and engineering that has developed rapidly over the past 30 years. This rapid development is a result of the significant advances in digital computer technology and integrated–circuit fabrication. DSP processors are a diverse group, most share some common features designed to support fast execution of the repetitive, numerically intensive computat...

Three decades ago, theoretical physicists suggested that the controlled recovery of charges could result in electronic circuitry whose power dissipation approaches thermodynamic limits, growing at a significantly slower pace than the fCV 2 rate for CMOS switching power. Early engineering research in this field, which became generally known as adiabatic computing, focused on the asymptotic energ...

Reducing Power dissipation is one of the crucial problems in today’s scenario. So this dissipation has become a bottleneck in the design of high speed synchronous systems which are operating at high frequency. Clock signals have been a great source of Power. Design can be made on the basis of Clock gating approach to reduce the consumption of clock’s signal switching power which is the foremost...