VII Zusammenfassung VIII Selbstständigkeitserklärung IX Chapter 1: Introduction 1

China’s military planners like to claim that in overall terms, the PLA is technologically inferior if compared with its potential adversaries. Such inferiority will continue in the foreseeable future, even though the People’s Liberation Army (PLA) has made some progress in modernizing its weaponry in recent years. On the other hand, the strategic principles of the PLA have undergone a major shi...

This paper describes a heuristic method for generating test patternsfor Programmable Logic Arrays (PLAs). Exploiting the regular structure of PLAs, both random and deterministic test-pattern generation techniques are combined to achieve coverage o f crosspoint defects. Patterns to select or deselect product terms are generated through direct inspection of an array; test paths to an observable o...

In this paper a novel methodology to achieve fault tolerance in VLSI Array Processors is proposed. A “Fence” based approach is adopted in which the logic array is partitioned and spares are distributed along the boundary of the active array. The emulator as in conventional fault tolerance techniques takes care of fault mapping and reconfiguration. The latency, reconfiguration interconnect lengt...

This paper describes an implementation of a novel systolic array for sequence alignment on the SPLASH reconfigurable logic array. The systolic array operates in two phases. In the first phase, a sequence comparison array due to Lopresti [2] is used to compute a matrix of distances which is stored in local RAM. In the second phase, the stored distances are used by the alignment array to produce ...

The design of a I-input and a ?-input 4-valued logic gate is described. These gatcs can be used to implement cells of a gate array, with the benefit of having prograrnriiabk functionality and multiple-valued logic input and output lincs. Programmable fimctionality allows any or the four billion functions of a '-input 4-valued logic gate to be implemented by thc samc cell, and multiplc-valucd hg...

Architecture: We investigate an architecture with all memory information on one side of the array, leaving computation on the other to achieve speed and compactness. The array consists of a column of CLB’s, interconnected by a Self-Routing Network. The network (Omega) routes data packets on the basis of their content. An 32 CLB array is 1.8Kx15K sq.lambda. With asynchronous signalling, logic-bl...

Power consumption from logic circuits, interconnections, dock distribution, on chip memories, and off chip driving in CMOS VLSI is estimated. Estimation methods are demonstrated and verified. An estimate tool is created. Power consumption distribution between ~ I I ~ I T O M ~ C ~ ~ O I W , clock distribution, logic gates, memories, and off chip driving are analyzed by examples. Comparisons are...

In this paper a high-performance 1-D DCT processor is shown. It is based on a FFT algorithm that benefits from complex residue arithmetic to reduce the number of operations required. The array is based on the Quadratic Residue Number System (QRNS) which enables the implementation of complex adders (multipliers) with only two modular adders (multipliers). Thus, the number of additions and multip...