Today’s product demand and mix changes requiring reconfiguration of cells in each period of a multi-period planning horizon, This paper proposes a mixed-integer non-linear programming model for reconfigurable CMS design to meet changes in product mix & demand in each period of a multi-period planning horizon. The proposed model, to the best of author’s knowledge, is the most comprehensive model...

A previous hierarchical fault tracing method for combinational circuits which requires only CAD layout data in the CAD-linked electron beam test system is expanded as applicable to sequential circuits. The characteristics in the method remains unchanged that allows us to trace a fault hierarchically from the top level cell to the lowest primitive cell and from the primitive cell to the transist...

Metal price is one of the most important parameters in the calculation of cut- off grade. The cut- off grade has the main role in determination of mine layout. Mine layout actuates mineable reserve, mine life and economic profitability. Not considering the uncertainty in metal prices can lead to a non-optimal layout. In this paper optimum underground mine layout is determined by expected utilit...

In this paper, we investigated a one-dimensional compactor based on a 45°-shear line technique with jogs insertion for a cell layout. The compactor can be connected off line from current commercial layout tools, such as Tanner Pro’s L-Edit, Cadence’s Virtuoso or Springsoft’s Laker, using the CIF format. A data structure of edge-linked adjacent matrix is constructed for easy implementation in ou...

FPGA is a 2D array of configurable logic blocks. Packing is to pack logic elements into device specific configurable logic blocks for subsequent placement. The traditional fixed delay model of inter and intra cluster delays used in packing does not represent post-placement delays and often leads to sub-optimal solutions. This paper presents a new layout driven packing algorithm, named LDPack, b...

This paper presents the complete design methodology of a very low-voltage ∆Σ third-order modulator from highlevel specifications down to layout. Behavioral models taking into account cell non-idealities are developed and used to map performance specifications to lower levels. Emphasis has been made on eventual design reuse through design plans and layout templates in a layout-oriented circuit d...

As semiconductor technology advances into the nanoscale era, optical effects such as channel narrowing, corner rounding or line-end pullback are critical to accomplish circuit yield specifications. It is well-demonstrated that layout regularity reduces the increasing impact of process variations on circuit performance and reliability. The purpose of this paper is to present the layout design of...

We describe two ongoing compiler projects for high performance architectures at the University of Maryland being developed using the Stanford SUIF compiler infrastructure. First, we are investigating the impact of compilation techniques for eliminating synchronization overhead in compiler-parallelized programs running on software distributed-shared-memory (DSM) systems. Second, we are evaluatin...

We report the design of a 112 Gb/s radiation-hardened (RH) optical transceiver applicable to intra-satellite interconnects. The chipset comprises vertical-cavity surface-emitting laser (VCSEL) driver and transimpedance amplifier (TIA) integrated circuits (ICs) with four channels per die, which are adapted for flip-chip assembly into mid-board optics (MBO) module. ICs designed in IHP 130 nm SiGe...