This paper describes and evaluates the results obtained in implementing three methods of precise interrupts in pipeline processors in-order instruction completion, the reorder buffer, and the reorder buffer with bypass paths. Due to the limited scope of this paper, two other methods of implementing precise interrupts the history buffer and future file are not investigated. An interrupt is defin...

Several high-bandwidth network interfaces use Interrupt Coalescence (IC), i.e., they generate a single interrupt for multiple packets sent or received in a short time interval. IC decreases the per-packet interrupt processing overhead. However, IC also introduces queueing delays and alters the “dispersion” (i.e., interarrival time spacing) of packet pairs or trains. In this work, we first expla...