In the past, acceptance of Distributed Shared Memory (DSM) systems suuered because of poor performance. Performance has primarily been limited by the availability of an interconnect media whose properties are similar to those required by a DSM system. In an eeort to compensate for inappropriate interfaces, sig-niicant research has been devoted to maximizing the utilization of the available inte...

Chip Interconnect delay and power is a primary criterion in the design of an Integrated Circuit because of its close connection to the speed of IC. Interconnect Buffers in VLSI circuits is the most widespread procedure used to decrease power and delay but they outcome in high Delay and power dissipation, thereby degrading the performance (i.e.) operating speed of an integrated circuit. Use of b...

This paper examines the recently introduced chargebased capacitance measurement (CBCM) technique through use of a three-dimensional (3-D) interconnect simulator. This method can be used in conjunction with simulation at early process development stages to provide designers with accurate parasitic interconnect capacitances. Metal to substrate, interwire, and interlayer capacitances are each disc...

In the deep-submicron era, interconnect delays are becoming one of the most important factors that can affect performance in the VLSI design. Many state-of-the-art research in high level synthesis try to consider the effect of interconnect delays. These research indeed achieve better performance compared with traditional ones which ignore interconnect delays. When applications contain large loo...

The widely applied Structure-Preserving Reduced-order Interconnect Macromodeling (SPRIM) algorithm cannot retain the reciprocity or block structure of circuit matrices original system, being inherent to RCL circuits; and consequently it is harder synthesize a Passive Algorithms (PRIMA) model into practical circuit. In order overcome this deficiency, paper proposes an improved SPRIM maintain fea...

In this paper, discontinuous interconnect lines are modelled and analyzed as a cascaded line composed of many uniform interconnect lines. The system transfer functions of respective uniform interconnect lines are determined, followed by its time domain response. Since the time domain response expression is a transcendental form, the waveform expression is reconfigured as an approximated linear ...

Interconnect diagnosis is an important problem in very large scale integration (VLSI), multi-chip module (MCM) and printed circuit board (PCB) production. The problem is to detect and locate all the shorts, opens and stuck-at faults among a set of nets using the minimum number of parallel tests. In this paper, we present worst-case optimal algorithms and lower bounds to several open problems in...

Asynchronous rather than synchronous interconnect has been a promising alternative for a large scale system to remove significant problems caused by global clock trees. Considering the vulnerability of asynchronous circuit to hazards, in this paper we investigate the occurrence of deadlocks on asynchronous 2-phase interconnect. Finally we explore the space of fault tolerance in the 2-phase inte...

Shorts and opens are the most common types of catastrophic defects in today's CMOS ICs. In this paper we show that an open in the interconnect wiring of a digital CMOS circuit, which permanently disconnects inputs of logic gates from their driver, can cause oscillation or sequential behavior. We present supporting experimental data collected by creating an interconnect open in a manufactured ch...

Cathode poisoning by chromium evaporation from the interconnects is one of major degradation mechanisms in SOFC. Coatings have proved to be very effective suppressing on interconnects. The quantification important for determining consumption interconnect and predicting lifetime interconnect. Chromium uncoated Ce/Co coated Crofer 22 APU reevaluated at 800°C. coatings steel sheets precut steels s...