نتایج جستجو برای: inter cell layout

تعداد نتایج: 1815053  

2010
David González González Mario García-Lozano Silvia Ruiz-Boque Joan J. Olmos

Effective interference management has been recognized by the industry and standardization bodies as a key enabler for 4G systems. This work is about static Inter-Cell Interference Coordination for OFDMA based cellular networks such as LTE. The majority of previous ICIC studies, both theoretical and simulation-based, have been conducted considering synthetic and/or small cellular layouts. In thi...

K. N. Nandurkar, , K. V. Chandratre, ,

In today’s economy, manufacturing plants must be able to operate efficiently and respond quickly to changes in the product mix and demand.[1] Layout design has a significant impact on manufacturing efficiency. Initially, it was treated as a static decision but due to improvements in technology, it is possible to rearrange the manufacturing facilities in different scenarios. The Plant layout...

1999
Makoto FURUIE Bao-Yu SONG Yukihiro YOSHIDA Takao ONOYE

| An array cell (AC) architecture for the layout design is described, which is dedicated to lowpower design by means of the NMOS 4-phase dynamic logic. An AC is constructed of (M N)+2 transistors so as to constitute each type of NMOS 4-phase logic gates. A graph theoretic approach is exploited in the layout design to reduce the layout area. A number of experimental results demonstrate the pract...

2012
Jatin N. Mistry John Biggs James Myers Bashir M. Al-Hashimi David Flynn

In this paper we present a physical layout methodology, called dRail, to allow power gated and non-power gated cells to be placed next to each other. This is unlike traditional voltage area layout which separates cells to prevent shorting of power supplies leading to impact on area, routing and power. To implement dRail, a modified standard cell architecture and physical layout is proposed. The...

2009
Marc Pons Francesc Moll Antonio Rubio Antonio González

Digital CMOS Integrated Circuits (ICs) suffer from serious layout features printability issues associated to the lithography manufacturing process. Regular layout designs are emerging as alternative solutions to reduce these ICs systematic subwavelength lithography failures. However, there is no metric to evaluate and compare the layout regularity of those regular designs. In this paper we prop...

Journal: :international journal of advanced design and manufacturing technology 0
vahid abedini behrouz arezou mohsen shakeri

sheet metal components design and manufacture need a great deal of experience and know-how. strip layout design is usually done with trial and error until best design for strip layout is finally achieved. knowledge for the system is formulated from plasticity theories, experimental results, and the empirical knowledge of field experts. in this paper, an algorithm which can automatically design ...

2004
Ke Cao Jiang Hu Mosong Cheng

In sub-wavelength lithography, light field Alt-PSM (Alternating Phase Shifting Mask) is an essential technology for poly layer printability. In a standard cell based design, the problem of obtaining Alt-PSM compliance for an individual cell layout has been solved well [3]. However, placing Alt-PSM compliant cells together can not guarantee Alt-PSM compliance of the entire chip/block layout due ...

2004
Reinhold Heckmann Reinhard Wilhelm

Both the quality of the results of TEX s formula layout algorithm and the complexity of its description in the TEXbook are hard to beat The algorithm is verbally described as an imperative program with very complex control ow and complicated manipulations of the data structures representing formulae In a forthcoming textbook we describe TEX s formula layout algorithm as a functional program tra...

پایان نامه :وزارت علوم، تحقیقات و فناوری - دانشگاه فردوسی مشهد - دانشکده مهندسی 1391

با توجه به توسعه و پیشرفت مدارهای الکترونیکی کاشته شده در مغز، امکان شناسایی و پیشگیری سریع از وقوع صرع وتشنج، میسرگردیده‏‏است. پردازنده داخل قشری مغز ، بخشی از یک مدار واسط کاشته‏ شده در مغز می‏باشد. وظیفه این پردازنده، آشکارسازی پیک سیگنال‏های عصبی برای ارسال ساده‏تر اطلاعات با نرخ بیت کمتر و توان مصرفی کمتر به محیط بیرون مغز می‏باشد. برای آشکارسازی پیک‏ها از عملگر انرژی تیگر ( teo) به عنوان ...

2001
Michael Yu Wang Diana M. Pelinescu

This paper addresses two major issues in fixture layout design: (1) to determine the feasible fixture configurations that satisfy fundamental requirements such as kinematic localization and total fixturing (formclosure) and (2) to evaluate the acceptable fixture designs on several quality criteria and select the optimal fixture appropriate with practical demands. The performance objectives cons...

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