We address the problem of control synthesis for pipelined data paths. Two basic control schemes are possible: datastationary and time-stationary. In this work, we consider the latter approach. We developed an approach to automatically synthesize time-stationarycontrollers for pipelined data paths produced by high level synthesis tools. A highly optimized FSM controller is implemented using eith...

This work focuses on the construction of power estimators for the high-level synthesis of analog front-ends and more precisely on power estimators for analog filters. A power estimator is a function that returns an estimated value for the power consumed by a functional block when given some relevant specifications as input and without knowing the detailed implementation of the block. After some...

In this paper we study possible improvements of high-level (architectural) synthesis processes. We allow the designer to indicate a set of bindings between behaviour and structure in order to add some of the designer's knowledge to the design process. These bindings can be used to exclude ineecient designs. The remaining design space may then be studied in more detail, using uniied backtracking...

VHDL permits design descriptions with communicating multiple processes and provides signal assignments and wait statements to facilitate coordination and communication among the processes. These constructs lead to concise behavioral speciications but make controller generation in high level synthesis diicult. Current work on synthesis from VHDL restricts the behavioral subset, excluding or limi...

At the behavioral level, large power saving is possible by shutting down unused operations, which is commonly referred to as power management. However, on the other hand, operation scheduling has a significant impact on the potential for power saving via power management. In this paper, we present an integer linear programming (ILP) model for the simultaneous application of operation scheduling...

The systems supporting signal and image applications process large amount of data. That involves an intensive use of the memory which becomes the bottleneck of systems. Memory limits performances and represents a significant proportion of total consumption. In the development high level synthesis tool called GAUT Low Power, we are interested in the synthesis of the memory unit. In this work, we...

This paper describes a novel technique for formal synthesis and exempliies the main ideas using the high level synthesis task | scheduling. The novelty of the approach is based on the fact, that arbitrary scheduling algorithms can be embedded within a formal framework to automatically achieve guaranteed correct implementations. Two realistic examples are used to emphasize its applicability and ...

Hardware design methods come closer to software engineering. Proven techniques are further ahead than common awareness of them. Behavioral Synthesis means hardware compilation rather than CAD: Hardware compilation from register-transfer level sources or even from high-level programs like C sources. The programmer “programs” by himself the hardware he needs. This has become reality by novel dyna...

is concerned with algorithm design and mapping the algorithm onto hardware. High-level synthesis, which until now was used only in industrial laboratories and universities, is evolving from its embryonic state to practical use in product design. Commercial products now address logic-level synthesis, which is rapidly gaining user acceptance. Logic synthesis systems manipulate a Boolean-level or ...

In this paper we argue that the trend towards system design requires to teach high-level design, in both lectures and design projects. High-level synthesis and hardware-software codesign are two key words. The main part of our paper presents our experiences with a design project where we used the MIMOLA software system for high-level synthesis of a oating-point pocket calculator chip. We descri...